The XCR22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Xilinx offers the XCR22LV10 that offers high speed and low power in a 3V implementation.
The XCR22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.

*Industry's first TotalCMOS™ SPLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and high speed
-Static current of less than 75 μA
-Dynamic current substantially below that of competing devices
-Pin-to-pin delay of only 7.5 ns
*True Zero Power device with no turbo bits or power down schemes
*Function/JEDEC map compatible with Bipolar, UVCMOS, EECMOS 22V10s
*Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP)
-24-pin TSOIC–uses 93% less in-system space than a 28-pin PLCC
-24-pin SOIC
-28-pin PLCC with standard JEDEC pinout
*Available in commercial and industrial operating ranges
*Advanced 0.5μ E2CMOS process
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Varied product term distribution with up to 16 product terms per output for complex functions
*Programmable output polarity
*Synchronous preset/asynchronous reset capability
*Security bit prevents unauthorized access
*Electronic signature for identification
*Design entry and verification using industry standard CAE tools
*Reprogrammable using industry standard device programmers

XCR22V10-10SO24, XCR22V10-7SO24, XCR22V10-10VO24C, XCR22V10-7VO24C

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 The MC34063A by Analog Integrations Corporation, an improved second source over the
industrial standard MC34063A, is a monolithic control circuit containing the primary functions required for DC/DC converters.
The device consists of an internal temperature compensated reference, comparator, controlled duty cycle oscillator with an active current limit circuit, driver and high current output switch. This device is specifically designed to be incorporated in stepdown, step-up and voltage-inverting applications with a minimum number of external components.
The ±1.8% internal reference and low quiescent current of 1.6mA are among the improvements of the device over the competition.

* 3V to 30V Input Voltage Operation.
* Internal 1.6A Peak Current Switch.
* Internal ±1.8% Reference.
* Low Quiescent Current at 1.6mA.
* Frequency Operation from 100Hz to 100KHz.
* Current Limiting.

* Saver for Cellular phones
* DC-DC Converter Module


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The PALCE16V8 is an advanced PAL device built with low-power, high-speed,
electrically-erasable CMOS technology. It is functionally compatible with all 20-pin GAL devices. The macrocells provide a universal device architecture. The PALCE16V8 will directly replace the PAL16R8 and PAL10H8 series devices, with the exception of the PAL16C1.
 The PALCE16V8 utilizes the familiar sum-of-products (AND/OR) architecture that allows users to implement complex logic functions easily and efficiently. Multiple levels of combinatorial logic can always be reduced to sum-of-products form, taking advantage of the very wide input gates available in PAL devices. The equations are programmed into the device through floatinggate
cells in the AND logic array that can be erased electrically.
 The fixed OR array allows up to eight data product terms per output for logic functions. The sum of these products feeds the output macrocell. Each macrocell can be programmed as registered or combinatorial with an activehigh or active-low output. The output configuration is determined by two global bits and one local bit controlling four multiplexers in each macrocell.
 AMD’s FusionPLD program allows PALCE16V8 designs to be implemented using a wide variety of popular industry-standard design tools. By working closely with the FusionPLD partners, AMD certifies that the tools provide accurate, quality support. By ensuring that thirdparty tools are available, costs are lowered because a designer does not have to buy a complete set of new tools for each device. The FusionPLD program also greatly reduces design time since a designer can use a tool that is already installed and familiar.

* Pin and function compatible with all 20-pin GAL devices
* Electrically erasable CMOS technology provides reconfigurable logic and full testability
* High-speed CMOS technology
— 5-ns propagation delay for “-5” version
— 7.5-ns propagation delay for “-7” version
* Direct plug-in replacement for the PAL16R8 series and most of the PAL10H8 series
* Outputs programmable as registered or combinatorial in any combination
* Peripheral Component Interconnect (PCI) compliant
* Programmable output polarity
* Programmable enable/disable control
* Preloadable output registers for testability
* Automatic register reset on power up
* Cost-effective 20-pin plastic DIP, PLCC, and SOIC packages
* Extensive third-party software and programmer support through FusionPLD partners
* Fully tested for 100% programming and functional yields and high reliability
* 5 ns version utilizes a split leadframe for improved performance


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