DESCRIPTION
The UCD9220 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop
management with flash memory and a serial interface to support configuration, monitoring and management.
The UCD9220 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.
To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.
TI has also developed multiple complementary power stage solutions – from discrete drives in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD9k family of system power controllers.

FEATURES
*Fully Configurable Multi-Output and Multi-Phase Non-Isolated DC/DC PWM Controller
*Controls Up To Two Voltage Rails and Up To Four Phases
*Supports Switching Frequencies Up to 2MHz With 250 ps Duty-Cycle Resolution
*Up To 1mV Closed Loop Resolution
*Hardware-Accelerated, 3-Pole/3-Zero Compensator With Non-Linear Gain for Improved Transient Performance
*Supports Multiple Soft-Start and Soft-Stop Configurations Including Prebias Start-up
*Supports Voltage Tracking, Margining and Sequencing
*Supports Current and Temperature Balancing for Multi-Phase Power Stages
*Supports Phase Adding/Shedding for Multi-Phase Power Stages
*Sync In /Out Pins Align DPWM Clocks Between Multiple UCD9220 Devices
*12-Bit Digital Monitoring of Power Supply Parameters Including:
-Input Current and Voltage
-Output Current and Voltage
-Temperature at Each Power Stage
*Multiple Levels of Overcurrent Fault Protection:
-External Current Fault Inputs
-Analog Comparators Monitor Current Sense Voltage
-Current Digitally Monitored
*Over and Undervoltage Fault Protection
*Overtemperature Fault Protection
*Enhanced Nonvolatile Memory With Error Correction Code (ECC)
*Device Operates From a Single Supply With an Internal Regulator Controller That Allows Operation Over a Wide Supply Voltage Range
*Supported by Fusion Digital Power™ Designer, a Full Featured PC Based Design Tool to Simulate, Configure, and Monitor Power Supply Performance.

APPLICATIONS
*Industrial/ATE
*Networking Equipment
*Telecommunications Equipment
*Servers
*Storage Systems
*FPGA, DSP and Memory Power

UCD9220RGZR, UCD9220RGZT

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Description
The ISL62386 controller generates supply voltages for battery-powered systems. The ISL62386 includes two pulse-width modulation (PWM) controllers, adjustable from 0.6V to 5.5V, and two linear regulators, LDO5 and LDO3, that generate a fixed 5V output and a fixed 3.3V output respectively. Each can deliver up to 100mA. The Channel 2 switching regulator will automatically take over the LDO5 load when programmed to 5V output. This provides a large power saving and boosts efficiency. The ISL62386 includes on-board power-up sequencing, one power-good (PGOOD) output, digital soft-start, and an internal soft-stop output discharge that prevents negative voltages on shutdown.
The patented R3 PWM control scheme provides a low jitter system with fast response to load transients. Light-load efficiency is improved with period-stretching discontinuous conduction mode (DCM) operation. To eliminate noise in audio frequency applications, an ultrasonic DCM mode is included, which limits the minimum switching frequency to approximately 28kHz.
The ISL62386 is available in a 32 Ld 5x5 TQFN package, and can operate over the extended temperature range (-10°C to +100°C).

Features
*High Performance R3 Technology
*Fast Transient Response
*±1% Output Voltage Accuracy: -10°C to +100°C
*Two Fully Programmable Switch-Mode Power Supplies with Independent Operation
*Programmable Switching Frequency
*Integrated MOSFET Drivers and Bootstrap Diode
*Fixed +3.3V LDO Output with Enable Control
*Fixed +5V LDO with Automatic Switchover to SMPS2
*Internal Soft-Start and Soft-Stop Output Discharge
*Wide Input Voltage Range: +5.5V to +25V
*Full and Ultrasonic Pulse-Skipping Mode
*Power-Good Indicator
*Overvoltage, Undervoltage and Overcurrent Protection
*Thermal Monitor and Protection
*Pb-Free (RoHS Compliant)

Applications
*Notebook and Sub-Notebook Computers
*PDAs and Mobile Communication Devices
*3-Cell and 4-Cell Li+ Battery-Powered Devices
*General Purpose Switching Buck Regulators

ISL62386HRTZ, ISL62386HRTZ-T

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Description
The CA3228 is a monolithic integrated circuit designed as an automotive speed-control system.
The system monitors vehicle speed and compares it to a stored reference speed. Any deviation in vehicle speed causes a servo mechanism to open or close the engine throttle as required to eliminate the speed error. The reference speed, set by the driver, is stored in a 9-bit counter.
The reference speed can be altered by the ACCEL and COAST driver commands. The ACCEL command causes the vehicle to accelerate at a controlled rate; the COAST command disables the servo, thereby forcing the vehicle to slowdown. Application of the brake disables the servo and places the system in the standby mode while the RESUME command returns the vehicle to the last stored speed.
Vehicle speed and driver commands are inputs to the integrated circuit via external sensors. Actuators are needed to convert the output signals into the mechanical action necessary to control vehicle speed.
The CA3228 is supplied in a 24 lead dual-in-line plastic package (E suffix). Refer to AN7326 for application information.

Features
*Low Power Dissipation
*I2L Control Logic
*Power-On Reset
*On-Chip Oscillator for System Time Reference
*Single Input Line for Operator Commands
*Amplitude Encoded Control Signals
*Transient Compensated Input Commands
*Controlled Acceleration Mode
*Internal Redundant Brake and Low-Speed Disable
*Braking Disable

Applications
*Automotive Speed Control
*Residential and Industrial Heating and Cooling Controls
*Industrial AC and DC Motor Speed Control
*Applications Requiring Acceleration and Deceleration Control

CA3228E

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DESCRIPTION
The UCD9240 is a multi-rail, multi-phase synchronous buck digital PWM controller designed for non-isolated DC/DC power applications. This device integrates dedicated circuitry for DC/DC loop management with flash memory and a serial interface to support configurability, monitoring and management.
The UCD9240 was designed to provide a wide variety of desirable features for non-isolated DC/DC converter applications while minimizing the total system component count by reducing external circuits. The solution integrates multi-loop management with sequencing, margining, tracking and intelligent phase management to optimize for total system efficiency. Additionally, loop compensation and calibration are supported without the need to add external components.
To facilitate configuring the device, the Texas Instruments Fusion Digital Power™ Designer is
provided. This PC based Graphical User Interface offers an intuitive interface to the device. This tool allows the design engineer to configure the system operating parameters for the application, store the configuration to on-chip non-volatile memory and observe both frequency domain and time domain simulations for each of the power stage outputs.
TI has also developed multiple complementary power stage solutions – from discrete drives in the UCD7k family to fully tested power train modules in the PTD family. These solutions have been developed to complement the UCD9k family of system power controllers.

FEATURES
*Fully Configurable Multi-Output and Multi-Phase Non-Isolated DC/DC PWM
Controller
*Controls Up To Four Voltage Rails and Up To Eight Phases
*Supports Switching Frequencies Up to 2MHz With 250 ps Duty-Cycle Resolution
*Up To 1mV Closed Loop Resolution
*Hardware-Accelerated, 3-Pole/3-Zero Compensator With Non-Linear Gain for
Improved Transient Performance
*Supports Multiple Soft-Start and Soft-Stop Configurations Including Prebias Start-up
*Supports Voltage Tracking, Margining and Sequencing
*Supports Current and Temperature Balancing for Multi-Phase Power Stages
*Supports Phase Adding/Shedding for Multi-Phase Power Stages
*Sync In /Out Pins Align DPWM Clocks Between Multiple UCD9240 Devices
*Fan Monitoring and Control
*12-Bit Digital Monitoring of Power Supply Parameters Including:
– Input Current and Voltage
– Output Current and Voltage
– Temperature at Each Power Stage
*Multiple Levels of Overcurrent Fault Protection:
– External Current Fault Inputs
– Analog Comparators Monitor Current Sense Voltage
– Current Continually Digitally Monitored
*Over and Undervoltage Fault Protection
*Overtemperature Fault Protection
*Enhanced Nonvolatile Memory With Error Correction Code (ECC)
*Device Operates From a Single Supply With an Internal Regulator Controller That Allows
Operation Over a Wide Supply Voltage Range
*Supported by Fusion Digital Power™ Designer, a Full Featured PC Based Design
Tool to Simulate, Configure, and Monitor Power Supply Performance.

APPLICATIONS
*Industrial/ATE
*Networking Equipment
*Telecommunications Equipment
*Servers
*Storage Systems
*FPGA, DSP and Memory Power

UCD9240PFCR, UCD9240PFC

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DESCRIPTION
The M62500 is a semiconductor integrated circuit designed and developed as a deflection control of the CRT display monitor.
The built-in trigger mode oscillator allows stable PWM control to be gained against a wide range of change of external signals.
The M62500 provides a low supply voltage output malfunction preventive circuit (UVLO) and software start function optimum to horizontal output correction of monitor, high voltage drive and high voltage regulator.

FEATURES
*PWM output in synchronization with external signals
*Wide range of PWM control frequency
 15kHz to 150kHz
*The PWM output phase is adjustable against external signals
*Soft start
*Built-in low voltage output malfunction prevention circuit
 Start VCC>9V
 Stop VCC<6V

APPLICATION
CRT display monitor

M62500FP

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Description
The ispGDXVA architecture provides a family of fast, flexible programmable devices to address a variety of system-level digital signal routing and interface requirements including:
*Multi-Port Multiprocessor Interfaces
*Wide Data and Address Bus Multiplexing (e.g. 16:1 High-Speed Bus MUX)
*Programmable Control Signal Routing (e.g. Interrupts, DMAREQs, etc.)
*Board-Level PCB Signal Routing for Prototyping or Programmable Bus Interfaces
The devices feature fast operation, with input-to-output signal delays (Tpd) of 3.5ns and clock-to-output delays of 3.5ns.
The architecture of the devices consists of a series of programmable I/O cells interconnected by a Global Routing Pool (GRP).
All I/O pin inputs enter the GRP directly or are registered or latched so they can be routed to the
required I/O outputs.
I/O pin inputs are defined as four sets (A,B,C,D) which have access to the four MUX inputs
found in each I/O cell. Each output has individual, programmable I/O tri-state control (OE), output latch clockCLK), clock enable (CLKEN), and two multiplexer control (MUX0 and MUX1) inputs.
Polarity for these signals is programmable for each I/O cell. The MUX0 and MUX1 inputs control a fast 4:1 MUX, allowing dynamic selection of up to four signal sources for a given output.
A wider 16:1 MUX can be implemented with the MUX expander feature of each I/O and a propagation delay increase of 2.0ns.
OE, CLK, CLKEN, and MUX0 and MUX1 inputs can be driven directly from selected sets of I/O pins.
Optional dedicated clock input pins give minimum clockto- output delays.
CLK and CLKEN share the same set of I/O pins.
CLKEN disables the register clock when CLKEN = 0.
Through in-system programming, connections between I/O pins and architectural features (latched or registered inputs or outputs, output enable control, etc.) can be defined.
In keeping with its data path application focus, the ispGDXVA devices contain no programmable logic arrays.
All input pins include Schmitt trigger buffers for noise immunity.
These connections are programmed into the device using non-volatile E2CMOS technology.
Non-volatile technology means the device configuration is saved even when the power is emoved from the device.
In addition, there are no pin-to-pin routing constraints for 1:1 or 1:n signal routing.
That is, any I/O pin configured as an input can drive one or more I/O pins configured as
outputs.
The device pins also have the ability to set outputs to fixed HIGH or LOW logic levels (Jumper or DIP Switch mode).
Device outputs are specified for 24mA sink and 12mA source current (at JEDEC LVTTL levels) and can be tied together in parallel for greater drive.
On the ispGDXVA, each I/O pin is individually programmable for 3.3V or 2.5V output levels as described later.
Programmable output slew rate control can be defined independently for each I/O pin to reduce overall ground bounce and switching noise.
All I/O pins are equipped with IEEE1149.1-compliant Boundary Scan Test circuitry for enhanced testability.
In addition, in-system programming is supported through the Test Access Port via a special set of private commands.
The ispGDXVA I/Os are designed to withstand “live insertion” system environments.
The I/O buffers are disabled during power-up and power-down cycles.
When designing for “live insertion,” absolute maximum rating conditions for the Vcc and I/O pins must still be met.

Features
*IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY
-Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement
-“Any Input to Any Output” Routing -Fixed HIGH or LOW Output Option for Jumper/DIP Switch Emulation
-Space-Saving PQFP and BGA Packaging
-Dedicated IEEE 1149.1-Compliant Boundary Scan Test
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.3V Core Power Supply
-3.5ns Input-to-Output/3.5ns Clock-to-Output Delay
-250MHz Maximum Clock Frequency
-TTL/3.3V/2.5V Compatible Input Thresholds and Output Levels (Individually Programmable)
-Low-Power: 16.5mA Quiescent Icc
-24mA IOL Drive with Programmable Slew Rate Control Option
-PCI Compatible Drive Capability
-Schmitt Trigger Inputs for Noise Immunity
-Electrically Erasable and Reprogrammable
-Non-Volatile E2CMOS Technology
*ispGDXV™ OFFERS THE FOLLOWING ADVANTAGES
-3.3V In-System Programmable Using Boundary Scan Test Access Port (TAP)
-Change Interconnects in Seconds
*FLEXIBLE ARCHITECTURE
-Combinatorial/Latched/Registered Inputs or Outputs
-Individual I/O Tri-state Control with Polarity Control
-Dedicated Clock/Clock Enable Input Pins (two) or Programmable Clocks/Clock Enables from I/O Pins (20)
-Single Level 4:1 Dynamic Path Selection (Tpd = 3.5ns)
-Programmable Wide-MUX Cascade Feature Supports up to 16:1 MUX
-Programmable Pull-ups, Bus Hold Latch and Open Drain on I/O Pins
-Outputs Tri-state During Power-up (“Live Insertion” Friendly)
*DESIGN SUPPORT THROUGH LATTICE’S ispGDX DEVELOPMENT SOFTWARE
-MS Windows or NT / PC-Based or Sun O/S
-Easy Text-Based Design Entry
-Automatic Signal Routing
-Program up to 100 ISP Devices Concurrently
-Simulator Netlist Generation for Easy Board-Level Simulation

ISPGDX80VA-5T100
ISPGDX80VA-3T100

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Outline
This IC functions in a variety of CPU systems and other logic systems to generate a reset signal and reset the system accurately during momentary interruption or lowering of power supply voltage.
It also has a built-in watchdog timer for operation diagnosis.
This prevents the system from running wild by generating an intermittent reset pulse during system mis-operation.

Features
*Built-in watchdog timer
*Low minimum operating voltage VCC=0.8V typ.
*Both positive and negative logic reset output can be extracted
*Accurate detection of drop in power supply voltage
*Detection voltage has hysteresis
*Few external parts 1 capacitor
*Timer monitoring time can be varied by using an external resistor

MM1075XD
MM1075XF

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Description
The ispLSI 1016EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between all of these elements.
The ispLSI 1016EA features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port.
The ispLSI 1016EA offers non-volatile reprogrammability of the logic, as well as the interconnect
to provide truly reconfigurable systems.
A functional superset of the ispLSI 1016 architecture, the ispLSI 1016EA device adds user-selectable 3.3V or 5V I/O and open-drain output options.
The basic unit of logic on the ispLSI 1016EA device is the Generic Logic Block (GLB).
The GLBs are labeled A0, A1...B7 (Figure 1).
There are a total of 16 GLBs in the ispLSI 1016EA device.
Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and a dedicated input.
All of the GLB outputs are brought back into the GRP so that they can be connected to the
inputs of any other GLB on the device.

Features
* HIGH-DENSITY PROGRAMMABLE LOGIC
- 2000 PLD Gates
- 32 I/O Pins, One Dedicated Input
- 96 Registers
- High-Speed Global Interconnect
- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
- Functionally Compatible with ispLSI 1016E
* NEW FEATURES
- 100% IEEE 1149.1 Boundary Scan Testable
- ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
- User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (VCCIO Pin)
- Open-Drain Output Option
* HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
- fmax = 200 MHz Maximum Operating Frequency
- tpd = 4.5 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile
- 100% Tested at Time of Manufacture
- Unused Product Term Shutdown Saves Power
* IN-SYSTEM PROGRAMMABLE
- Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
- Reprogram Soldered Device for Faster Prototyping
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue Logic and Structured Designs
- Enhanced Pin Locking Capability
- Three Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Programmable Output Slew Rate Control to Minimize Switching Noise
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global Interconnectivity

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Description
 Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs.
Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin.
New data is available a short access time after each rising clock edge.
The FPGA generates the appropriate number of clock pulses to complete the configuration.
When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM.
When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA.
After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins.
New data is available a short access time after each rising clock edge.
The data is clocked into the FPGA on the following rising edge of the CCLK.
A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device.
The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.
All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.

Features
* In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs
- Endurance of 20,000 Program/Erase Cycles
- Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)
* IEEE Std 1149.1 Boundary-Scan (JTAG) Support
* JTAG Command Initiation of Standard FPGA Configuration
* Simple Interface to the FPGA
* Cascadable for Storing Longer or Multiple Bitstreams
* Low-Power Advanced CMOS FLASH Process
* Dual Configuration Modes
- Serial Slow/Fast Configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
* 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
* 3.3V or 2.5V Output Capability
* Design Support Using the Xilinx ISE™ Foundation™ Software Packages
* Available in PC20, SO20, PC44, and VQ44 Packages
* Lead-Free (Pb-Free) Packaging

XC18V04
XC18V02
XC18V01
XC18V512

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Construction
* Round varistor element, leaded
* Coating: phenolic resin
* Terminals: tinned copper wire

Features
* New automotive series for 42-V supply systems
* This series complies with the electrical requirements for the new 42-V board net as specified in draft standard ISO/TC22 WD42V-1E
* Stable protection level, minimum leakage current
* High resistance to cyclic temperature stress: 1000 cycles
* High operating temperature of up to 125˚C

Applications
* Reliable protection from inductive voltage spikes, e. g. in wiper and air vent motors, power windows, rear mirror, power seat and other servo drives

Taping
* All types available on tape upon request

B72210S1390K501
B72214S1390K501
B72220S1390K501

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