Description
 The TM54S816T is organized as 4-bank x 2097152-word x 16-bit(8Mx16), fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features
* Package: 400-mil 54-pin TSOP(II)
* JEDEC PC133/PC100 compatible
* Single 3.3V Power Supply
* LVTTL Signal Compatible
* Programmable
- CAS Latency (3 or 2 clocks)
- Burst Length (1,2,4, 8 & full page)
- Burst type (Sequential & Interleave)
* Burst read/write and burst read/single write operations capability
* Byte control(DQML and DQMU)
* Auto and Self Refresh
* 64ms refresh period (4K Refresh)
* 12-Row x 9-Column organization
* 4-Bank operation controlled by BA1,BA0
* Pin36 and 40 are “No Connected”
* Fully synchronous operation referenced to clock rising edge

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