Description
The OMAP-L137 is a Low-power applications processor based on an ARM926EJ-S™ and a C674x™ DSP core. It provides significantly lower power than other members of the  MS320C6000™ platform of DSPs.
The OMAP-L137 enables OEMs and ODMs to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance life through the maximum flexibility of a fully integrated mixed processor solution.
The dual-core architecture of the OMAP-L137 provides benefits of both DSP and Reduced Instruction Set Computer (RISC) technologies, incorporating a high-performance TMS320C674x DSP core and an ARM926EJ-S core.
The ARM926EJ-S is a 32-bit RISC processor core that performs 32-bit or 16-bit instructions and
processes 32-bit, 16-bit, or 8-bit data. The core uses pipelining so that all parts of the processor and memory system can operate continuously.
The ARM core has a coprocessor 15 (CP15), protection module, and Data and program Memory
Management Units (MMUs) with table look-aside buffers. It has separate 16K-byte instruction and 16K-byte data caches. Both are four-way associative with virtual index virtual tag (VIVT). The ARM core also has a 8KB RAM (Vector Table) and 64KB ROM.
The OMAP-L137 DSP core uses a two-level cache-based architecture. The Level 1 program cache (L1P) is a 32KB direct mapped cache and the Level 1 data cache (L1D) is a 32KB 2-way set-associative cache. The Level 2 program cache (L2P) consists of a 256KB memory space that is shared between program and data space. L2 also has a 1024KB ROM. L2 memory can be configured as mapped memory, cache, or combinations of the two. Although the DSP L2 is accessible by ARM and other hosts in the system, an additional 128KB RAM shared memory is available for use by other hosts without affecting DSP performance.
The peripheral set includes: a 10/100 Mb/s Ethernet MAC (EMAC) with a Management Data Input/Output (MDIO) module; two inter-integrated circuit (I2C) Bus interfaces; 3 multichannel audio serial port (McASP) with 16/12/4 serializers and FIFO buffers; 2 64-bit general-purpose timers each configurable (one configurable as watchdog); a configurable 16-bit host port interface (HPI); up to 8 banks of 16 pins of general-purpose input/output (GPIO) with programmable interrupt/event generation modes, multiplexed with other peripherals; 3 UART interfaces (one with RTS and CTS); 3 enhanced high-resolution pulse width modulator (eHRPWM) peripherals; 3 32-bit enhanced capture (eCAP) module peripherals which can
be configured as 3 capture inputs or 3 auxiliary pulse width modulator (APWM) outputs; 2 32-bit enhanced quadrature pulse (eQEP) peripherals; and 2 external memory interfaces: an synchronous and SDRAM external memory interface (EMIFA) for slower memories or peripherals, and a higher speed memory interface (EMIFB) for SDRAM.
The Ethernet Media Access Controller (EMAC) provides an efficient interface between the OMAP-L137 and the network. The EMAC supports both 10Base-T and 100Base-TX, or 10 Mbits/second (Mbps) and 100 Mbps in either half- or full-duplex mode. Additionally an Management Data Input/Output (MDIO) interface is available for PHY configuration.
The HPI, I2C, SPI, USB1.1 and USB2.0 ports allow the OMAP-L137 to easily control peripheral devices and/or communicate with host processors.
The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each of the peripherals, see the related sections later in this document and the associated peripheral reference guides.
The OMAP-L137 has a complete set of development tools for both the ARM and DSP. These include C compilers, a DSP assembly optimizer to simplify programming and scheduling, and a Windows™ debugger interface for visibility into source code execution.

Features
*Applications
- Industrial Control
- USB, Networking
- High-Speed Encoding
- Professional Audio
*Software Support
– TI DSP/BIOS™
– Chip Support Library and DSP Library
*Dual Core SoC
– 300-MHz ARM926EJ-S™ RISC MPU
– 300-MHz C674x™ VLIW DSP
*ARM926EJ-S Core
– 32-Bit and 16-Bit (Thumb®) Instructions
– DSP Instruction Extensions
– Single Cycle MAC
– ARM® Jazelle® Technology
– EmbeddedICE-RT™ for Real-Time Debug
*ARM9 Memory Architecture
*C674x Instruction Set Features
– Superset of the C67x+™ and C64x+™ ISAs
– 2400/1800 C674x MIPS/MFLOPS
– Byte-Addressable (8-/16-/32-/64-Bit Data)
– 8-Bit Overflow Protection
– Bit-Field Extract, Set, Clear
- Normalization, Saturation, Bit-Counting
- Compact 16-Bit Instructions
*C674x Two Level Cache Memory Architecture
– 32K-Byte L1P Program RAM/Cache
– 32K-Byte L1D Data RAM/Cache
– 256K-Byte L2 Unified Mapped RAM/Cache
– Flexible RAM/Cache Partition (L1 and L2)
– 1024K-Byte L2 ROM
*Enhanced Direct-Memory-Access Controller 3 (EDMA3):
– 2 Transfer Controllers
– 32 Independent DMA Channels
– 8 Quick DMA Channels
– Programmable Transfer Burst Size
*TMS320C674x™ Floating Point VLIW DSP Core
– LSouapdp-oSrttore Architecture With Non-Aligned
– 64 General-Purpose Registers (32 Bit)
– Six ALU (32-/40-Bit) Functional Units
– Two Multiply Functional Units
– Instruction Packing Reduces Code Size
– All Instructions Conditional
– Hardware Support for Modulo Loop Operation
– Protected Mode Operation
– Exceptions Support for Error Detection and Program Redirecrion
*128K-Byte RAM Shared Memory
*Two External Memory Interfaces:
– EMIFA
– EMIFB
*Three Configurable 16550 type UART Modules:
– UART0 With Modem Control Signals
– 16-byte FIFO
– 16x or 13x Oversampling Option
*LCD Controller
*Two Serial Peripheral Interfaces (SPI) Each With One Chip-Select
*Multimedia Card (MMC)/Secure Digital (SD) Card Interface with Secure Data I/O (SDIO)
*Two Master/Slave Inter-Integrated Circuit (I2C Bus™)
*USB 1.1 OHCI (Host) With Integrated PHY (USB1)
*USB 2.0 OTG Port With Integrated PHY (USB0)
– USB 2.0 High-/Full-Speed Client
– USB 2.0 High-/Full-/Low-Speed Host
– End Point 0 (Control)
– End Points 1,2,3,4 (Control, Bulk, Interrupt or ISOC) Rx and Tx
*Three Multichannel Audio Serial Ports:
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 28 Serial Data Pins
- Supports TDM, I2S, and Similar Formats
- DIT-Capavle (McASP2)
- FIFO buffers for Transmit and Receive
*10/100 Mb/s Ethernet MAC (EMAC):
– IEEE 802.3 Compliant (3.3-V I/O Only)
– RMII Media Independent Interface
– Management Data I/O (MDIO) Module
*One Host-Port Interface (HPI) With 16-Bit-Wide Muxed Address/Data Bus For High Bandwidth
*Real-Time Clock With 32 KHz Oscillator and Separate Power Rail
*One 64-Bit General-Purpose Timer (Configurable as Two 32-Bit Timers)
*One 64-Bit General-Purpose Timer (Watch Dog)
*Three Enhanced Pulse Width Modulators (eHRPWM):
– Dedicated 16-Bit Time-Base Counter With Period And Frequency Control
– 6 Single Edge, 6 Dual Edge Symmetric or 3 Dual Edge Asymmetric Outputs
– Dead-Band Generation
– PWM Chopping by High-Frequency Carrier
– Trip Zone Input
*Three 32-Bit Enhanced Capture Modules (eCAP):
- Configurable as 3 Capture Inputs or 3 Auxiliary Pulse Width Modulator(APWM)outputs
- Single Shot Capture of up to Four Event Time-Stamps
*Two 32-Bit Enhanced Quadrature Encoder Pulse Modules (eQEP)
*256-Ball Pb-Free Plastic Ball Grid Array (PBGA) [ZKB Suffix], 1.0-mm Ball Pitch
*Commercial or Extended Temperature

OMAPL137ZKB3, XOMAPL137ZKB3

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Chip Summary
The nanoNET chip is a low-power, highly integrated mixed signal chip utilizing Nanotron’s unique wireless Chirp Spread Spectrum (CSS) communication technology.
This innovative modulation technique permits the development of chips that have extremely low power consumption, operate over a wide range of temperatures, and perform effortlessly in robust wireless networks operating in the 2.45 GHz ISM band.
This chip offers an ideal solution for battery powered applications that require a reliable and extremely long operating lifetime, such as several years.
For communication over the air, CSS uses Upchirps and Downchirps with a symbol duration of Tsymbol = 1 μs and an effective bandwidth of Bchirp = 64 MHz.
A wide variety of systems and applications can be developed with this novel technology, with the additional advantage of being able to select from data rates of either 500 kbps, 1 Mbps, or 2 Mbps.
Conveniently, only a minimal number of external components are required to build a fully operational bi-directional communication node.

Target Applications
Industries that can benefit from nanoNET's robust, reliable communication include, but are not limited to:
+ Active RFID
+ Industrial Control and Monitoring
+ Home Automation
+ Meter and Sensor Reading

Key Features
+ Provides a single chip solution for a 2.45 GHz ISM band RF transceiver
+ Allows unregulated 2.4 V ... 3.6 V supply voltage
+ Includes an integrated SPI (slave mode only)
+ Includes an integrated microcontroller management function
+ Provides a maximum data rate of 2 Mbps
+ Provides a maximum range for LOS (without interferers) at 900 m outdoors and 60 m
indoors (with optimal conditions)
+ Uses an effective chirp bandwidth of 64 MHz
+ Receiver sensitivity is -92 dBm @ 1 Mbps
+ Carrier to Interference is C/I = -3…0 dB @ C = -82 dBm
+ Processing gain is 17 dB
+ Current consumption is 35 mA (RX), 78 mA (TX) @ 8 dBm
+ Standby current with active RTC is 1.5 μA
+ Allows an operating temperature range of between -40° C to +85° C
+ Includes an integrated 4 channel digital I/O
+ Includes an integrated MAC controller
+ Provides a 32.768 kHz clock for microcontrollers
+ Includes a programmable clock output at digital output

TAG low-power

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