'link' related articles 2

  1. 2009/04/18 TSS461E - VAN Data Link Controller
  2. 2007/12/18 DS90CR213 - 21-Bit Channel Link - 66 MHz
Cost optimization in car manufacturing is of extreme importance today. Solutions to this problem often implies the use of more advanced and intelligent electronic circuits.
The TSS461E is a circuit which allows the transfer of all the status information needed in a car or truck over a single low-cost wire pair, thereby, minimizing the electrical wire usage.
It can be used to interconnect powerful functions (ABS, dashboard, power train control) and to control and interface car body electronics (lights, wipers, power window, etc.).
The TSS461E is fully compliant with the ISO standard 11519-3. This standard supports a wide range of applications such as low-cost remote control switches, typically used for lamp control; complex, highly-autonomous, distributed systems like engine controls, which require fast and secure data transfers.
The TSS461E is a microprocessor-interfaced line controller for mid-to-high complexity bus-masters and listeners like injection/ignition control calculators, dashboard controllers and car stereo or mobile telephone CPUs.
The microprocessor interface consists of a 256-bytes of RAM and the register area is divided into 11 control registers, 14 channel register sets and 128 bytes of general purpose RAM, used as a message storage area, and a 6-source maskable interrupt.
The circuit operates in RAM using DMA techniques, controlled by the channel and control registers. This allows virtually any microprocessor to interface with ease to the TSS461E, and to use the free RAM as a scratch pad.
Messages are encoded in enhanced Manchester code, and an optional pulsed code for use with an optical or radio link, at a maximum bit rate of 1 Mbit/s. The TSS461E analyzes the messages received or transmitted according to 6 different criteria including some higher level checks.
In addition, the bus interface has three separate inputs with automatic source diagnosis and selection, allowing for multibus listening or the automatic selection of the most reliable source at any time if several line receivers are connected to the same bus.

*Fully Compliant to VAN Specification ISO/11519.3
*Handles All Specified Module Types
*Handles All Specified Message Types
*Handles Retransmission of Frames on Contention and Errors
*3 Separate Line Inputs with Automatic Diagnosis and Selection
*1 Mbit/s Maximum Transfer Rate
*Normal or Pulsed (Optical and Radio Mode) Coding
*Intel®, NEC®, Texas Instruments® and Motorola® Compatible 8-bit Microprocessor Interface
*Multiplexed Address and Data Bus
*Idle and Sleep Modes
*128 Bytes of General-purpose RAM
*DMA Capabilities for Message Handling
*14 Identifier Registers with All Bits Individually Maskable
*6-source Maskable Interrupt Including an Interrupt-on-reset to Detect Glitches on the Reset Pin
*Integrated Crystal or Resonator Oscillator with Internal Baud Rate Generator and Buffered Clock Output
*Single +5V Power Supply
*0.5 mm CMOS Technology
*SOP 24 Packaging


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General Description
The DS90CR213 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR214 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 66 MHz, 21 bits of TTL data are
transmitted at a rate of 462 Mbps per LVDS data channel.
Using a 66 MHz clock, the data throughput is 1.386 Gbit/ (173 Mbytes/s).
The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 21-bit wide data and one clock, up to 44 conductors are required. With the Channel Link chipset as few as 9 conductors (3 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides an 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cable’s smaller form factor.
The 21 CMOS/TTL inputs can support a variety of signal combinations. For example, 5 4-bit nibbles (byte + parity) 2 9-bit (byte + 3 parity) and 1 control.

* 66 MHz Clock Support
* Up to 173 Mbytes/s bandwidth
* Low power CMOS design (<610 mW)
* Power-down mode (<0.5 mW total)
* Up to 1.386 Gbit/s data throughput
* Narrow bus reduces cable size and cost
* 290 mV swing LVDS devices for low EMI
* PLL requires no external components
* Low profile 48-lead TSSOP package
* Rising edge data strobe
* Compatible with TIA/EIA-644 LVDS Standard


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