FUNCTIONAL DESCRIPTION
The DLO31F-series device is a gated delay line oscillator. The device produces a stable square wave which is synchronized with the falling edge of the Gate Input (GB). The frequency of oscillation is given by the device dash number (See Table). The two outputs (C1,C2) are in phase during oscillation, but return to opposite logic levels when the device is disabled.

FEATURES
*Continuous or keyable wave train
*Synchronizes with arbitrary gating signal
*Fits standard 14-pin DIP socket
*Low profile
*Auto-insertable
*Input & outputs fully TTL interfaced & buffered
*Available in frequencies from 2MHz to 40MHz

DLO31F-2, DLO31F-2.5, DLO31F-3, DLO31F-3.5, DLO31F-4, DLO31F-4.5

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GENERAL DESCRIPTION
The XRT6164 is a CMOS analog chip intended for general purpose line interface applications at bit rates up to 1.544Mbps (T1). It contains both receive and transmit circuitry in a 16-pin dual-in-line plastic package. The receiver is designed for short line applications having a cable loss up to 10dB measured at the half bit rate. The transmitter has open collector line driver outputs that are capable of handling up to 40mA. When used in conjunction with either XRT6165 or XRT6166, the chip set provides a 64Kbps codirectional interface as specified in CCITT G.703.

FEATURES
*Single 5V Supply
*CCITT G.703 Compatible When Used With Either XR-T6165 or XR-T6166
*Low Power
*TTL Compatible Digital Inputs and Outputs
*Links Remote Equipment at Distances up to 500 Meters Without Equalization
*Receive Data Comparator Threshold Storage Provides Ping-Pong Operation Capability
*Loss of Signal Alarm
*Dual Matched Driver Outputs

APPLICATIONS
*Data Adaption Unit (DAU)
*General Purpose TTL Compatible Line Interface

XRT6164CP, XRT6164CD

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FUNCTIONAL DESCRIPTION
The 3D7418 Programmable 8-Bit Silicon Delay Line product family consists of 8-bit, user-programmable CMOS silicon integrated circuits. Delay values, programmed either via the serial or parallel interface, can be varied over 255 equal steps ranging from 250ps to 5.0ns inclusively. Units have a typical inherent (zero step) delay of 12ns to 17ns (See Table 1). The input is reproduced at the output without inversion, shifted in time as per user selection.
The 3D7418 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7418 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL programmable delay lines. It is offered in a standard 16-pin auto-insertable DIP and a space saving surface mount 16-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Increment range: 0.25 through 5.0ns
*Delay tolerance: 1% (See Table 1)
*Temperature stability: ±3% typical (0C-70C)
*Vdd stability: ±1% typical (4.75V-5.25V)
*Minimum input pulse width: 10% of total delay
*Programmable via 3-wire serial or 8-bit parallel interface

3D7418-0.25, 3D7418-0.5, 3D7418-1, 3D7418-2, 3D7418-3, 3D7418-4, 3D7418-5

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FUNCTIONAL DESCRIPTION
The 1518-series device is a fixed, single-input, fiveoutput, passive delay line. The signal input (IN) is reproduced at the outputs (T1-T5) in equal increments. The delay from IN to T5 (TD) and the characteristic impedance of the line (Z) are determined by the dash number. The rise time (TR) of the line is 30% of TD, and the 3dB bandwidth is given by 1.05 / TD. The device is available in a 14-pin SMD with two pinout options.
Part numbers are constructed according to the scheme shown at right. For example, 1518-101-500A is a 100ns, 50W delay line with pinout code A. Similarly, 1518-151-501 a is 150ns, 500W delay line with standard pinout.

FEATURES
*5 taps of equal delay increment
*Delays to 200ns
*Low profile
*Epoxy encapsulated
*Meets or exceeds MIL-D-23859C

1518-5-10IN, 1518-10-10IN, 1518-15-10IN, 1518-100-10IN, 1518-200-10IN
TAG DELAY, line, SMD

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FUNCTIONAL DESCRIPTION
The 3D7323 Triple Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains three matched, independent delay lines. Delay values can range from 6ns through 6000ns. The input is reproduced at the output without inversion, shifted in time as per the user-specified dash number. The 3D7323 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy.
The all-CMOS 3D7323 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 8-pin auto-insertable DIP and a space saving surface mount 8-pin SOIC.

FEATURES
*All-silicon, low-power CMOS technology
*TTL/CMOS compatible inputs and outputs
*Vapor phase, IR and wave solderable
*Auto-insertable (DIP pkg.)
*Low ground bounce noise
*Leading- and trailing-edge accuracy
*Delay range: 6 through 6000ns
*Delay tolerance: 2% or 1.0ns
*Temperature stability: ±3% typ (-40C to 85C)
*Vdd stability: ±1% typical (4.75V to 5.25V)
* Minimum input pulse width: 20% of total delay
*14-pin DIP available as drop-in replacement for hybrid delay lines

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Description
 The PBL 3766 Subscriber Line Interface Circuit (SLIC) is a monolithic integrated circuit, manufactured in 75 V bipolar technology.
The PBL 3766 SLIC facilitates the design of cost effective, high performance on-premises (ONS) analog line interface ards for PABX systems and terminal adapters.
Small package size and few required external components result in a miniaturized design.
The PBL 3766 programmable, constant current loop feed system can operate with battery supply voltages between -24 V and -58 V.
The SLIC incorporates loop current and ring trip detection functions as well as a ring relay driver.
The two- to four-wire and four- to two-wire voice frequency (vf) signal conversion, i.e. the hybrid function, is provided by the SLIC in conjunction with either a conventional or a programmable CODEC/filter.
The PBL 3766 package is a 22 pin, plastic dual-in-line (batwing) or a 28-pin, plastic j-leaded chip carrier (PLCC).
The differences between PBL 3766 and PBL 3766/6 are the specifications for balance, output offset voltage, and insertion loss.

Key Features
* Low cost
* Few external components
* Programmable, constant current loop feed
* Line feed characteristics independent of battery supply variations
* -24 V to -58 V battery supply voltage range
* Detectors
– programmable loop current detector
– ring trip detector
* Ring relay driver
* Hybrid function with conventional or programmable CODEC/filters
* Line terminating impedance, complex or real, set by a simple external network or controlled by a programmable CODEC/filter
* Idle noise typ. -83 dBmp, typ. 7 dBrnC
* Low on-hook power dissipation: 20 mW @ -28 V, 35 mW @ -48 V
* Tip-ring open circuit state for subscriber loop power denial
* On-hook transmission

PBL3766N
PBL3766/6N
PBL3766QN
PBL3766/6QN

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The 9-channel IMP5219 SCSI terminator is part of IMP's family of highperformance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator terminator approach.
The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required.
The IMP architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs. Reduced component count is inherent with the IMP5219.
The IMP5219 architecture tolerates marginal system designs.
A key improvement offered by the IMP5219 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable lengths and impedance.
Frequently, this situation is not controlled by the peripheral or host designer.
For portable and configurable peripherals, the IMP5219 can be placed in a sleep mode with an active LOW disable signal.
Quiescent current is typically 375μA and output are in a high impedance state when disabled.

Key Features
* Ultra-Fast response for Fast-20 SCSI applications
* Hot swap compatible
* 35MHz channel bandwidth
* 3.5V operation
* Less than 3pF output capacitance
* Sleep-mode current less than 375μA
* Thermally self limiting
* No external compensation capacitors
* Implements 8-bit or 16-bit (wide) applications
* Compatible with active negation drivers (60ma/channel)
* Compatible with passive and active terminations
* Approved for use with SCSI 1, 2, 3 and UltraSCSI

IMP5219CDW
IMP5219CDWT
IMP5219CPW
IMP5219CPWT

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XR-T7288 - Line Interface

Exar 2007/12/06 11:20

FEATURES
* Fully Integrated 2.048Mbits/s Line Interface
* Intended For Use In Systems That Must Comply With CCITT Specifications G.703, G.823, I.431,
G.732, G.735, G.739
* Pin-Selectable 75W or 120W Operation
* Monolithic Clock Recovery
* Low Power Dissipation:
100mW for 120W Twisted Pair, Typical
108mW for 75W Coaxial, Typical
* Minimal External Circuitry Required
* Robust Frequency Acquisition/Phase-Locked Loop
* Pin-Selectable HDB3 Encoder and Decoder
* Loopback Modes for Fault Isolation
* Multiple Link-Status and Alarm Features
* Single-Rail/Dual-Rail Interface

GENERAL DESCRIPTION
The XR-T7288 CEPT1 Line Interface is an integrated circuit that provides a 2.048 Mbits/s line interface to either twisted-pair or coaxial cable as specified in CCITT requirements G.703, G.823, I.431, G.732, and G.735 G.739. The device performs receive pulse regeneration, timing recovery, and transmit pulse driving functions. The XR-T7288 device is manufactured by using low-power CMOS technology and is available in a 28-pin, plastic DIP or in a 28-pin, plastic SOJ package for surface mounting.
The XR-T7288 device is functionally compatible with the LC1135B device.


XR-T7288IP
XR-T7288IW

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FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 0.75ns through 7000ns
• Delay tolerance: 2% or 0.5ns
• Temperature stability: ±2% typical (-40C to 85C)
• Vdd stability: ±1% typical (3.0V-3.6V)
• Minimum input pulse width: 15% of total delay
• 14-pin Gull-Wing available as drop-in replacement for hybrid delay lines

FUNCTIONAL DESCRIPTION
 The 3D3220 10-Tap Delay Line product family consists of fixed-delay CMOS integrated circuits. Each package contains a single delay line, tapped and buffered at 10 points spaced uniformly in time. Tap-to-tap (incremental) delay values can range from 0.75ns through 700ns. The input is reproduced at the outputs without inversion, shifted in time as per the user-specified dash number.
 
 The 3D3220 is TTL- and CMOS-compatible, capable of driving ten 74LS-type loads, and features both rising- and falling-edge accuracy. The all-CMOS 3D3220 integrated circuit has been designed as a reliable, economic alternative to hybrid TTL fixed delay lines. It is offered in a standard 14-pin auto-insertable DIP and space saving surface mount 14-pin SOIC and 16-pin SOL packages.

APPLICATION NOTES
OPERATIONAL DESCRIPTION The 3D3220 ten-tap delay line architecture is shown in Figure 1. The delay line is composed of a number of delay cells connected in series. Each delay cell produces at its output a replica of the signal present at its input, shifted in time. The delay cells are matched and share the same compensation signals, which minimizes tap-to-tap delay deviations over temperature and supply voltage variations.

INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low) of operation may adversely impact the specified delay accuracy of the particular device. The reasons for the dependency of the output delay accuracy on the input signal characteristics are varied and complex. Therefore a Maximum and an Absolute Maximum operating input frequency and a Minimum and an Absolute Minimum operating pulse width have been specified.

OPERATING FREQUENCY
The Absolute Maximum Operating Frequency specification, tabulated in Table 1, determines the highest frequency of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable duty cycle distortion. The Maximum Operating Frequency specification determines the highest frequency of the delay line input signal for which the output delay accuracy is guaranteed.

 To guarantee the Table 1 delay accuracy for input frequencies higher than the Maximum Operating Frequency, the 3D3220 must be tested at the user operating frequency. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency of operation. The programmed delay accuracy of the device is guaranteed, therefore, only at the user specified input frequency. Small input frequency variation about the selected frequency will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

OPERATING PULSE WIDTH
 The Absolute Minimum Operating Pulse Width (high or low) specification, tabulated in Table 1, determines the smallest Pulse Width of the delay line input signal that can be reproduced, shifted in time at the device output, with acceptable pulse width distortion. The Minimum Operating Pulse Width (high or low) specification determines the smallest Pulse Width of the delay line input signal for which the output delay accuracy tabulated in Table 1 is guaranteed.

 To guarantee the Table 1 delay accuracy for input pulse width smaller than the Minimum Operating Pulse Width, the 3D3220 must be tested at the user operating pulse width. Therefore, to facilitate production and device identification, the part number will include a custom reference designator identifying the intended frequency and duty cycle of operation. The programmed delay accuracy of the device is guaranteed, therefore, only for the user specified input characteristics. Small input pulse width variation about the selected pulse width will only marginally impact the programmed delay accuracy, if at all. Nevertheless, it is strongly recommended that the engineering staff at DATA DELAY DEVICES be consulted.

3D3220-xx
3D3220G-XX
3D3220D-xx
3D3220S-xx

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* AM26LS32A Devices Meet or Exceed the Requirements of ANSI TIA/EIA-422-B, TIA/EIA-423-B, and ITU Recommendations V.10 and V.11
* AM26LS32A Devices Have ±7-V Common-Mode Range With ±200-mV Sensitivity
* AM26LS33A Devices Have ±15-V Common-Mode Range With ±500-mV Sensitivity
* Input Hysteresis . . . 50 mV Typical
* Operate From a Single 5-V Supply
* Low-Power Schottky Circuitry
* 3-State Outputs
* Complementary Output-Enable Inputs
* Input Impedance . . . 12 kΩ Min
* Designed to Be Interchangeable With Advanced Micro Devices AM26LS32 and AM26LS33

description
 The AM26LS32A and AM26LS33A devices are quadruple differential line receivers for balanced
and unbalanced digital data transmission. The enable function is common to all four receivers
and offers a choice of active-high or active-low input. The 3-state outputs permit connection
directly to a bus-organized system. Fail-safe design ensures that, if the inputs are open, the
outputs always are high.
 
 Compared to the AM26LS32 and the AM26LS33, the AM26LS32A and AM26LS33A incorporate an additional stage of amplification to improve sensitivity. The input impedance has been increased, resulting in less loading of the bus line. The additional stage has increased propagation delay; however, this does not affect interchangeability in most applications.

 The AM26LS32AC and AM26LS33AC are characterized for operation from 0°C to 70°C. The AM26LS32AI is characterized for operation from –40°C to 85°C. The AM26LS32AM and AM26LS33AM are characterized for operation over the full military temperature range of –55°C to 125°C.

AM26LS32AI AM26LS33AC AM26LS32AM AM26LS33AM AM26LS33ACDRG4 AM26LS33ACN
AM26LS33ACNE4 AM26LS33AMFKB AM26LS33AMJ AM26LS33AMJB AM26LS33AMWB
5962-7802003M2A 5962-7802003MEA 5962-7802003MFA 5962-7802004M2A 5962-7802004MEA
5962-7802004MFA AM26LS32ACD AM26LS32ACDE4 AM26LS32ACDR AM26LS32ACDRE4
AM26LS32ACN AM26LS32ACNE4 AM26LS32ACNSR AM26LS32ACNSRG4 AM26LS32AID
AM26LS32AIDE4 AM26LS32AIDR AM26LS32AIDRE4 AM26LS32AIN AM26LS32AINE4 AM26LS32AMFKB AM26LS32AMJ AM26LS32AMJB AM26LS32AMWB AM26LS33ACD
AM26LS33ACDE4 AM26LS33ACDG4 AM26LS33ACDR AM26LS33ACDRE4

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