'ip' related articles 1

  1. 2008/05/16 AL3000 - IP Frame Routing Processor

Overview
 The AL3000 provides all the necessary functions to implement IP Routing and Network Management for the RoX-II bus based Fast Ethernet and Gigabit Ethernet Switching System. The AL3000 is designed to interface to the Motorola PowerPC 800 Series, although the AL3000 could easily interface with any 32-bit microprocessor (non-PCI bus) with glue logic.
The AL3000 integrates high performance IPv4 Routing/Switching and Network Management engines.
These engines perform the following major functions:
* Routing Engine
- Four Quality of Service (QoS) Queues that support programmable weighted round-robin or strict priority to feed high-speed L3/L4 search engines
- IPv4 parser that classifies the frames and processes IP exception handling
- Routing Table Search function that performs L3/L4 search supporting 131,000 route entries, performs route table aging and maintains usage counters
- IP Field Replacement function that performs L2/L3/L4 field replacements and re-calculates L3/L4 checksums
- IP Route Trace function that provides frame header information to the CPU
* Network Management Engine
- Provides MAC services for the CPU to transmit and receive Ethernet frames to and from the RoX-II bus via high-speed DMA channels
- Gathers the MAC address updates in real-time for Bridge MIB support
- In conjunction with RoX-II bus Ethernet switch devices, provides Spanning- Tree support
- Provides access to all the internal registers of the RoX-II bus switch devices and their associated PHY devices
- Provides Ethernet related (EtherType), PHY related, and RMON MIB network\ statistics counters (48 counters per port)
The Routing Engine in the AL3000 pulls frames from RoX-II bus based switching devices, such as the AL126 or AL1022, according to the four priority queue control rules, and queues them to the search engine.
Network Management and other trapped frames (such as BPDU, GARP, etc.) are directly queued to the CPU DMA.
If a route entry is found, then all frame modification functions for IP routing are performed by the Field Replacement function.
Once fields are replaced, all L3/L4 checksums are updated, TTL decremented, and a new L2 FCS value is generated.
As a frame is routed, a frame header (first 64 bytes) can be sent to the CPU through a DMA channel for Router management or diagnostic applications.
Once a frame is routed, it is queued to one of the output ports of the RoX-II bus switching devices, and transmitted according to the new QoS priority classification.
Routed frames can also be sent to the CPU for forwarding to the WAN.
The AL3000 provides access to all registers and MAC address tables on RoX-II bus switching devices via remote register access commands.
The AL3000 also provides all the network statistic counters to support RMON groups 1 through 4 (EtherStats, History, History Control, Alarm) as well as Ethernet-like MIB.

Feature
- Provides routing functions to Allayer’s RoX-II bus Ethernet Switching devices
- Supports up to 32 Fast Ethernet or dual Gigabit ports on the RoX-II bus
- High performance Network (Layer 3) and Transport (Layer 4) address look-up engine
- Layer 2-, 3-, or 4-flow packet classification
- Programmable key search based on MAC and IP source and destination address, TCP socket, UDP socket or IP protocol number
- Supports up to 131,072 individual host route entries
- Supports 802.1q priority schemes and provides four Quality of Service (QoS) queues
- Provides Network Address Translation (NAT) per route database entry
- Provides support for IP Proxy Services with remappng of Layer 4 Socket replacements
- Programmable entry aging via internal timers and via external real-time clock
- Re-assigns VLAN tag and priority for each routed frame
- Programmable replacement of MAC and/or IP fields with associated Layer 3 and Layer 4 check-sum recalculation
- Supports 802.3ad port aggregation
- Supports virtually unlimited physical interfaces and as many logical interfaces as software is capable
- Congestion control for each physical interface and the overall routing engine
- Packet bandwidth control for each Layer 3 or Layer 4 flow
- Layer 3 buffer pool of up to 1024 frames
- Provides Ethernet, Bridge, and RMON MIB support for RoX II bus devices
- Six high-speed DMA engines
- 0.25 micron, 2.5V / 3.3V CMOS technology
- 456-pin BGA package

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