Description
The M25P10-A is a 1 Mbit (128 Kbit x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

Features
*1 Mbit of Flash memory
*Page Program (up to 256 bytes) in 1.4 ms (typical)
*Sector Erase (256 Kbit) in 0.65 s (typical)
*Bulk Erase (1 Mbit) in 1.7 s (typical)
*2.3 to 3.6 V single supply voltage
*SPI bus compatible serial interface
*50 MHz Clock rate (maximum)
*Deep Power-down mode 1 μA (typical)
*Electronic signatures
–JEDEC standard two-byte signature (2011h)
–RES instruction, one-byte signature (10h), for backward compatibility
*More than 20 years’ data retention
*Packages
–ECOPACK® (RoHS compliant)

M25P10-AVMN6TP/X, M25P10-AVMP6TP/X, M25P10-AVMB6TP/X

DESCRIPTION
The CXD1969 is an ‘Plug & Play’ and OpenCableTMCableCARDTM interface controller IC designed for use withOpenCableTM compliant CableCARDTMmodules. It performs the communication interface between a host microcontrollerand the CableCARDTM. The IC communicates to the Hosteither by a 68k-type or I2C connection. Communicationbetween the CXD1969 and the CableCARDTMis highly efficient due to the inclusion of a fully integrated hardware Physicallayer.
MPEG2 Transport Stream interfaces are fully programmable ensuring compatibility to commonly used Front End demodulators and MPEG2 decoders.
A SCTE 28 compliant software stack is also available for this device.

FEATURES
*PC Card Interface
-Fully integrated CableCARDTM interface.
-Support for generic PC Cards.
-Supports 3V3 modules (VPP either 3V3 or 5V)
-Integrated Physical layer with 1Kbyte buffers.
*Host Interface
-68k-type host bus interface
-27MHz or 33MHz operating frequency.
-I2C host bus interface.
-100kHz or 400kHz operation.
-Maskable/programmable interrupt capability.
-3V3 logic levels.
*OOB Interface
-Supports SCTE 28 Bidirectional OOB I/F.
*Transport Stream Interfaces
-Accepts MPEG2 compliant TS.
-SCTE28 compliant parallel TS interfaces to/from POD Card.
-TS interface from tuner (up to 72Mbits/s).
-Serial TS interface to downstream device (up to 72Mbits/s).
-Four serial input and output modes.
*Miscellaneous
-Integrated PLL for serial TS.
-5V compatible I/Os.
-LQFP 100-pin package.

APPLICATIONS
*iDTV
*Set Top Box
*Personal Video Recorder (PVR)

Description
The MT9171 (DSIC) and MT9172 (DNIC) are pin for pin compatible replacements for the MT8971 and MT8972, respectively. They are multi-function devices capable of providing high speed, full duplex digital transmission up to 160 kbit/s over a twisted wire pair.
They use adaptive echo-cancelling techniques and transfer data in (2B+D) format compatible to the ISDN basic rate. Several modes of operation allow an easy interface to digital telecommunication networks including use as a high speed limited distance modem with data rates up to 160 kbit/s. Both devices function identically but with the DSIC having a shorter maximum loop reach specification. The generic "DNIC" will be used to reference both devices unless otherwise noted. The MT9171/72 is fabricated in Zarlink’s ISO2-CMOS process.

Features
*Full duplex transmission over a single twisted pair
*Selectable 80 or 160 kbit/s line rate
*Adaptive echo cancellation
*Up to 3 km (9171) and 4 km (9172)
*ISDN compatible (2B+D) data format
*Transparent modem capability
*Frame synchronization and clock extraction
*Zarlink ST-BUS compatible
*Low power (typically 50 mW), single 5 V supply

Applications
*Digital subscriber lines
*High speed data transmission over twisted wires
*Digital PABX line cards and telephone sets
*80 or 160 kbit/s single chip modem

MT9171/72AE, MT9171/72AN, MT9171/72AP, MT9171/72APR, MT9171/72ANR
MT9171/72AE1, MT9171/72AP1, MT9171/72AN1, MT9171/72APR1, MT9171/72ANR1

Description
 The PBL 3766 Subscriber Line Interface Circuit (SLIC) is a monolithic integrated circuit, manufactured in 75 V bipolar technology.
The PBL 3766 SLIC facilitates the design of cost effective, high performance on-premises (ONS) analog line interface ards for PABX systems and terminal adapters.
Small package size and few required external components result in a miniaturized design.
The PBL 3766 programmable, constant current loop feed system can operate with battery supply voltages between -24 V and -58 V.
The SLIC incorporates loop current and ring trip detection functions as well as a ring relay driver.
The two- to four-wire and four- to two-wire voice frequency (vf) signal conversion, i.e. the hybrid function, is provided by the SLIC in conjunction with either a conventional or a programmable CODEC/filter.
The PBL 3766 package is a 22 pin, plastic dual-in-line (batwing) or a 28-pin, plastic j-leaded chip carrier (PLCC).
The differences between PBL 3766 and PBL 3766/6 are the specifications for balance, output offset voltage, and insertion loss.

Key Features
* Low cost
* Few external components
* Programmable, constant current loop feed
* Line feed characteristics independent of battery supply variations
* -24 V to -58 V battery supply voltage range
* Detectors
– programmable loop current detector
– ring trip detector
* Ring relay driver
* Hybrid function with conventional or programmable CODEC/filters
* Line terminating impedance, complex or real, set by a simple external network or controlled by a programmable CODEC/filter
* Idle noise typ. -83 dBmp, typ. 7 dBrnC
* Low on-hook power dissipation: 20 mW @ -28 V, 35 mW @ -48 V
* Tip-ring open circuit state for subscriber loop power denial
* On-hook transmission

PBL3766N
PBL3766/6N
PBL3766QN
PBL3766/6QN

Features
• Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards
• Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2)
• Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane)
• Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz)
• Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, or 0.1 Hz
• Supports automatic hitless reference switching and short term holdover during loss of reference inputs
• Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g. 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs
• Programmable output synthesizers (P0, P1) generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3)
• Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
• Configurable input to output delay and output to output phase alignment
• Configurable through a serial interface (SPI or I2C)
• DPLLs can be configured to provide synchronous or asynchronous clock outputs

Applications
• ITU-T G.8262 Line Cards which support 1GbE and 10GbE interfaces
• SONET line cards up to OC-192
• SDH line cards up to STM-64

ZL30131GGG
ZL30131GGG2

Description
 The M25P40 is a 4 Mbit (512 K × 8) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 8 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M25P40 in ECOPACK®
packages.
ECOPACK® packages are Lead-free and RoHS compliant.

Features
* 4 Mbit of Flash memory
* 2.3 V to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 50 MHz clock rate (maximum)
* Page Program (up to 256 bytes) in 1.5 ms (typical)
* Sector Erase (512 Kbit) in 1 s (typical)
* Bulk Erase (4 Mbit) in 4.5 s (typical)
* Deep Power-down mode 1 μA (typical)
* Hardware Write Protection: protected area size defined by three non-volatile bits (BP0, BP1 and BP2)
* Electronic signatures
– JEDEC standard two-byte signature (2013h)
– RES instruction, one-byte, signature (12h), for backward compatibility
* Packages
– ECOPACK® (RoHS compliant)

M25P40-VMN6TP/X
M25P40-VMP3G/X

GENERAL DESCRIPTION
 The A25L16P is a 16 Mbit (2M x 8) Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction. The memory is organized as 32 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 8192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

FEATURES
* 16 Mbit of Flash Memory
* Flexible Sector Architecture (4/4/8/16/32)KB/64x31 KB
* Bulk Erase (16 Mbit) in 20s (typical)
* Sector Erase (512 Kbit) in 1s (typical)
* Page Program (up to 256 Bytes) in 1.5ms (typical)
* 2.7 to 3.6V Single Supply Voltage
* SPI Bus Compatible Serial Interface
* 85MHz Clock Rate (maximum)
* Fast Read Dual Operation Instruction (3Bh/BBh)
* Deep Power-down Mode 1μA (typical)
* Top or Bottom Boot Block Configuration Available
* Electronic Signature
- JEDEC Standard Two-Byte Signature (2015h, Bottom; or 2025, Top)
- RES Instruction, One-Byte, Signature (14h)
* Package Options
- 8-pin SOP (209mil), 16-pin SOP, or 8-pin QFN
- All Pb-free (Lead-free) products are ROHS complaint

A25L16PTN-UF
A25L16PTQ-UF
A25L16PUN-F
A25L16PUQ-F

Overview
The two Channel Codec Filter PEB 2265 IOM-2 – SICOFI-2 is the logic continuation of a well-established family of Siemens Codec-Filter-ICs.
The IOM-2 – SICOFI-2 is a fully integrated PCM codec and filter fabricated in low power 1 mm CMOS technology for applications in digital communication systems.
Based on an advanced digital filter concept, the PEB 2265 provides excellent transmission performance and high flexibility.
The new filter concept (second generation) lends to a maximum of independence between the different filter blocks.
Each filter block can be seen like an one to one representative of the corresponding network element.
Only very few external components are needed, to complete the functionality of the IOM-2 – SICOFI-2.
The internal level accuracy is based on a very accurate bandgap reference.
The frequency behavior is mainly determined by digital filters, which do not have any fluctuations.
As a result of the new ADC and DAC concepts linearity is only limited by second order parasitic effects.
Although the device works with only one single 5-V supply there is a very good dynamic range available.

Features
• Single chip CODEC and FILTER to handle two CO- or PABX-channels
• Specification according to relevant CCITT, EIA and LSSGR recommendations
• Digital signal processing technique
• Programmable interface optimized to current feed SLICs and transformer solutions
• Four pin serial IOM-2 Interface
• Single power supply 5 V
• Advanced low power 1mm analog CMOS technology
• Standard 64-pin P-MQFP-64 package
• High performance Analog to Digital Conversion
• High performance Digital to Analog Conversion
• Programmable digital filters to adapt the transmission behavior especially for
– AC impedance matching
– transhybrid balancing
– frequency response
– gain
• Advanced test capabilities
– all digital pins can be tested within a boundary scan scheme (IEEE 1149.1)
– five digital loops
– four analog loops
– two programmable tone generators per channel
• Comprehensive development platform available
– software for automatic filter coefficient calculation – QSICOS
– Hardware development board – STUT 2465

Description
The i-Net TV FS450 is a fourth generation video scan converter.
It accepts many input resolutions, rates and formats and converts them to NTSC or PAL standards compliant with SMPTE-170M and CCIR-656 standards.
The chip has a programmable down scaler to fit the incoming resolution to the output display format.
The CCIR 656 ports allow external interface to other video chips.
The sync control block generates frame reset for genlocking other video components.
Required external components are minimal: a single 27 MHz oscillator or crystal and passive parts.
Digital progressive RGB inputs are downscaled or upscaled to the CCIR-656 horizontal pixel count and converted to the 656 format.
Vertical scaling and flicker filtering are done in 656 format.
The Flicker Filter is an advanced 2 dimensional filter that enhances text quality.
Flicker Filter and Sharpness parameters are programmable.
A digital video encoder that generates analog Y/C and Composite Video outputs is part of the
FS450.
For the composite output in NTSC, YNotch and C-Bandpass filters are available.
For RGB and YUV outputs, the encoder may be bypassed via a YUV to RGB transcoder for
SCART compatible video.
Scaling and clock parameters are automatically programmed by the driver, so the system remains genlocked with resolution changes.
The input parameters to the automatic scaling are TV viewable area, PAL or NTSC, and the GCC CRT Control Registers’ settings.
The FS451's encoder incorporates Macrovision 7 anti-copy protection technology.
All parameters can be read and written via the I2C compatible serial port.
Power is derived from +3.3V digital and analog supplies.
The package is 100-lead Quad Flat Pack (PQFP).

Features
* Flexible clock, data, and electrical interfaces allows glue-less digital interface to Intel 82810, National Geode and most other graphic controller chips ("GCC")
* Capable of operating as clock master, pseudo-master, and slave and supports both single and differential master clocks
* Programmable 2D scaling †
– Variable horizontal up and down scale
– Variable vertical downscale
– Output format can be tuned to the exact dimensions of the TV
* Advanced 2-D flicker filter †
* Supports Multiple Progressive Input Resolutions
– 640x480 to 1024x768
* Multiple Output Standards
– NTSC, NTSC-EIAJ, PAL-B/D/G/H/I/M/N
– Composite, S-Video, RGB SCART
– Composite Y-Notch and C-Bandpass Filters
* Genlock the GCC and incoming Video
– Provides the pixel clock to the GCC generated from a single 27MHz clock
– Provides frame synchronization output signal for other video components
* CCIR 656 outputs
* CCIR 656 input to the encoder
* 10-bit output D/A converters
* Macrovision 7 compliant (FS451 only)
* I2C‡ compatible port controls
* High level programming interface
* 100 pin PQFP package
* 3.3V operation
†Note: Covered under US Patent # 5,862,268 and/or patents pending.
‡Note: I2C is a registered trademark of Philips Corporation. The FS450 SIO bus is similar but not identical to Philips I2C bus.

Applications
* Internet Set Top Boxes
* PC video out (TV Ready PCs)
* Cable/DVD Player Set Top Boxes
* Web Appliances
* Information Appliances
* Video Kiosks

FS451
444-2131
444-2132

Description
TSSP4400 is a high intensity infrared emitting diode in GaAlAs on GaAs technology, molded in a clear, blue - grey tinted plastic package with spherical side view lens.
The device is spectrally matched to silicon photodiodes and phototransistors.

Features
*  High radiant power and high radiant intensity
*  Suitable for high pulse current operation
*  Low forward voltage
*  Angle of half intensity j = ± 22*
*  Peak wavelength * p = 925 nm
*  High reliability

Applications
High power infrared emitter in light curtains, light barriers, transmissive or reflective sensors in combination with PIN photodiodes or phototransistors.
Infrared remote control and free air transmission systems for long transmission distance and medium wide angle requirements in combination with PIN photo diodes or photo modules.
Suitable as replacement of CQX47.