General Description
AMI Semiconductor’s AMIS-721250 (PI6050D) contact image sensor (CIS) is a selectable 600 or 1200 dot per inch (dpi) resolution linear image sensor, which employs AMI Semiconductor’s proprietary CMOS image sensing technology. The sensor contains an on-chip output amplifier, power-down circuitry and parallel transfer features that are uniquely combined with the present-day active-pixel-sensor technology. The image sensors are designed to be cascaded end-to-end on a printed circuit board (PCB) and packaged in an image sensing module. Applications for the sensor array includes facsimiles, PC scanners, check readers, and office automation equipment.
Figure 1 is a block diagram of the sensor. Each sensor consists of 688 active pixels, their associated multiplexing switches, buffers, and an output amplifier circuit with a power down feature. The sensors pixel-pixel spacing is approximately 21.15μm. The size of each sensor without the scribe lines is 14560μm by 425μm.

Key Features
*600 or 1200dpi selectable resolutions
*344 or 688 image sensor elements (pixels)
*21.15μm (1200dpi) pixel center-to-center spacing (47.24dots/mm)
*On-chip amplifier
*Single 5.0V power supply
*3.3V input clocks
*3.0MHz maximum pixel rate
*Parallel / integrate and transfer
*Power-down circuit
*High sensitivity
*Low power
*Low noise

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DESCRIPTION
The WM8146 is a 12-bit analogue front end/digitiser IC, which processes and digitises the analogue output signals from linear CCD sensors at pixel sample rates of up to 6MSPS.
The device includes three analogue signal processing channels each of which contains Reset Level Clamping, Correlated Double Sampling and Programmable Gain and Offset adjust functions. The output from each of these channels is time multiplexed into a single high-speed 12-bit Analogue to Digital Converter. The digital output data is available in 8+4-bit wide multiplexed format, with no missing codes.
The WM8146 is controlled via a configurable serial interface, which is compatible with all of Wolfson’s imaging devices.
Powered from an analogue supply voltage of 5V and a digital interface supply of either 5V or 3.3V, the WM8146 typically only consumes 175mW when operating from 5V supplies.

FEATURES
*No missing codes guaranteed
*6MSPS sample rate
*Colour pixel by pixel or line by line sampling
*Monochrome sampling
*Selectable reset level clamp voltage
*Pixel by pixel or line by line clamping
*Correlated double sampling
*5-bit programmable gain amplifier
*8-bit + sign offset adjustment
*5V or 3.3V digital interface compatibility
*Serial control interface
*28-pin SOIC package

APPLICATIONS
*Flatbed scanners
*Multi-function peripherals
*Copier scanners
*CCD sensor interfaces

XWM8146CDW/V

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GENERAL DESCRIPTION
The CCD191 is a 6000 element line image sensor designed for scanning applications which require very high resolution, high sensitivity and very wide dynamic range.
Incorporation of on-chip anti-blooming and integration controls allow the CCD191 to be extremely useful in industrial measurement and control environments, or in environments where lighting conditions are difficult to control.
The CCD191 is a third generation device having an overall improved performance compared with first and second generation devices, including enhanced blue response and excellent low light level performance. The photoelement size is 10μm (0.39 mils) x 10μm (0.39 mils) on 10μm (0.39 mils) centers. The device is manufactured using Fairchild Imaging’s advanced chargecoupled device n-channel isoplanar buried-channel technology.

FEATURES
*6000 x 1 photosite array
*10 μm x 10μm photosites on 10μm pitch
*Anti-blooming and integration control
*Enhanced spectral response (particularly in the blue region)
*Excellent low-light-level performance
*Low dark signal
*Very high responsivity
*High speed operation
*Dynamic range typical: 15000:1
*Over 3 V peak-to-peak outputs
*Special selection available - consult factory
*AR coated window

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General Description
The Micron® Imaging MT9E001 is a 1/2.5-inch format CMOS active-pixel digital image
sensor with a pixel array of 3,264H x 2,448V.
It incorporates sophisticated on-chip camera functions such as windowing, mirroring, binning and skip modes, and snapshot mode.
It is programmable through a simple two-wire serial interface and has very low power consumption.
The MT9E001 digital image sensor features DigitalClarity® technology—Micron's breakthrough
low-noise CMOS imaging technology that achieves near CCD image quality (based on signal-to-noise ratio and low-light sensitivity) while maintaining the inherent size, cost, power consumption, and integration advantages of CMOS.

Features
* DigitalClarity® CMOS imaging technology
* Superior low-light performance
* Low dark current
* Simple two-wire serial interface
* Auto black level calibration
* Support for external mechanical shutter
* Support for external LED or Xenon flash
* High frame rate preview mode with arbitrary downsize scaling from maximum resolution
* Programmable controls: gain, frame size/rate, exposure, left-right and top-bottom image reversal, window size, and panning
* Data interface: parallel
* On-chip phase-locked loop (PLL)
* Bayer pattern down-size scaler
* Four channel shading correction (SC)

Applications
* Digital still cameras
* Cellular phones

MT9E001I12STC

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DESCRIPTION
 The MCM20014 is a fully integrated, high performance CMOS image sensor with features such as integrated timing control, and analog signal processing for digital imaging applications.
The part provides designers a complete imaging solution with a monolithic image capture and processing engine thus making it a true “camera on a chip”.
System benefits enable design of smaller, portable, low cost and low power systems.
Thereby making the product suitable for a variety of consumer applications including still/full motion imaging, security/surveillance, and automotive among others.
The imaging pixels are based on active CMOS pixels using pinned photodiodes that are realized using Motorola’s sub-micron ImageMOSTM technology.
The frame rate is completely adjustable from 0 to 30 frames per second without adjusting the system clock from 10Mhz.
Each pixel on the sensor is individually addressable allowing the user to control “Window of Interest” (WOI) panning and zooming, sub-sampling, resolution, exposure, gain, and other image processing features via a two pin I2C interface.
Programmable digital signal processing blocks included in the data path are bad-pixel replacement and noise compensation for image enhancement.
The sensor is run by supplying a single Master Clock.
The sensor output is 8 or 10 digital bits depending on output mode selected.

Features
* VGA resolution, active CMOS image sensor with square pixel unit cells
* 7.8μm pitch pixels with patented pinned photodiode architecture
* Bayer-RGB color filter array with optional micro lenses
* High sensitivity, quantum efficiency, and charge conversion efficiency
* Low fixed pattern noise / Wide dynamic range
* Antiblooming and continuous variable speed shutter
* Single master clock operation
* Digitally programmable via I2C interface
* Integrated on-chip timing/logic circuitry
* CDS sample and hold for suppression of low frequency and correlated reset noise
* 48X programmable variable gain to optimize dynamic range and facilitate white balance and iris adjustment
* 10-bit, pipelined algorithmic RSD ADC
* User selectable digital output formats:
* 8-bit companded data
* 10-bit linear data
* Column offset correction, and Bad Pixel Replacement for noise suppression
* Pixel addressability to support ‘Window of Interest’ windowing, resolution, and subsampling
* 30fps full VGA at 10Mhz Master Clock Rate
* Single 3.3V power supply
* 48 pin CLCC package

MCM20014IBMN
MCM20014IBB

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General Description
 Mimix Broadband’s 32.0-42.0 GHz GaAs MMIC sub-harmonic image reject mixer can be used as an upor down-converter.
The device has a conversion loss of 9.0 dB with 18.0 dB image rejection across the band.
I and Q mixer outputs are provided and an external 90 degree hybrid is required to select the desired sideband.
This MMIC uses Mimix Broadband’s 2 μm GaAs HBT device model technology, and is based upon electron beam lithography to ensure high repeatability and uniformity.
The chip has surface passivation to protect and provide a rugged part with backside via holes and gold metallization to allow either a conductive epoxy or eutectic solder die attach process. This device is well suited for Millimeter-wave Point-to-Point Radio, LMDS, SATCOM and VSAT applications.

Features
* Sub-harmonic Image Reject Mixer
* GaAs HBT Technology
* 9.0 dB Conversion Loss
* 18.0 dB Image Rejection
* 100% On-Wafer RF Testing
* 100% Visual Inspection to MIL-STD-883
* Method 2010

XM1003-BD-000V
XM1003-BD-EV1

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Description
 Peripheral Imaging Corporation PI3041A CIS, Contact Image Sensor, chip is a 300 dot per
inch resolution, linear array image sensor chip.
The sensor chip is processed using a CMOS Image Sensing Technology, a possession of ISPL (Image Sensor Product Line) group within AMIS.
Designed for cascading multiple chips in a series, the image sensor chips, uses a chipon- board process.
They are bonded end-to-end on a printed circuit board (PCB).
This bonding process allows the CIS module manufacturers to produce variable CIS module lengths in increments of the chip array lengths.
Hence, the modules are easily applied in a large number of document scanners, found in today’s facsimile market.
Examples are wide format maps and architectural drawings scanners down to the narrow width scanners, such as, those found in check readers, lotto tickets, entrance gates tickets, etc. This is not to exclude the many office automation equipments, which require an even more variety in scanning widths, as well as, those with special mechanically configurations.
Figure 1 is a block diagram of the imaging sensor chip. Each sensor chip consists of 96 detector elements, their associated multiplexing switches, buffers, and a chip selector.
The detector's element-to-element spacing is approximately 83.3 μm.
The size of each chip without scribe lines is 8080 μm by 380 μm.
Each sensor chip has 7 bonding pads.

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 The PM-36 is a fixed-function Codec device that delivers high speed JPEG compression/decompression of color and grayscale image data. An ISO standard for lossy image compression, JPEG can reduce the size of image data without a noticeable difference in image quality.
 This improves system performance of peripheral-based applications by reducing bandwidth and storage requirements. The PM-36 is ideal for high resolution imaging applications such as copiers, scanners, printers and multifunction peripherals, particularly in networked environments.

Benefits
• High Performance–JPEG Imaging Codec–Delivers sustained data rates of up to 110 MB per second
• Efficient Coding–four loadable Q-Tables and two loadable Huffman table pairs
• Highly Integrated–Internal Phase-Locked Loop (PLL)
• 3.3 Volt supply–5 Volt Tolerant I/O
• Standard Compliant–ISO IS 10918-1/10918-2 Benefits

Key Features
• Conforms to ISO IS 10918-1/10918-2 JPEG baseline for grayscale and color
• 80 MHz clock speed for sustained 80 MB/second throughput (Raster or Block mode operations)
• 110 MHz clock speed for sustained 110 MB/second throughput (Block mode operations only)
• 3.3 Volt power supply
• Four selectable quantization tables
• Two pairs of loadable Huffman tables
• Programmable code rate control
• Programmable code size control (single pass)
• Raster and block data formats
• Internal 256-byte buffers on input and output ports
• I/O modes supporting transfer rates up to 40 MHz (280 MB/per second)
• Internal Phase-Locked Loop (PLL)
• Horizontal 2:1 subsampling and upsampling support for 4:2:2 formats using 2 or 3 point filters (Raster mode operations only)


Description
- High Throughput
The PM-36 can sustain data rates of 80 or 110 MB per second to support real time operations. In addition, it implements two advanced features that maximize throughput and system performance:
• Programmable code rate control–This optional mode limits the encoded output data bandwidth to a predefined rate by dynamically reducing the quantization accuracy on a block-byblock basis, as required. This assures maximum throughput in high-speed peripherals.
• Programmable code size control–This mode allows definition of an upper limit for the size of the encoded output file so that it does not exceed a fixed memory buffer size. This is achieved in a single pass of the data, with no degradation in performance.

- Efficient Coding
The PM-36 features several advanced JPEG coding techniques for improved efficiency. Four loadable Q-tables are available for dynamic quantization control on a block-by-block basis. In addition, The PM-36 contains two loadable Huffman table pairs, which improves coding efficiency by allowing the system to use different encoding factors with out reprogramming the device.
- Highly Integrated
The PM-36 features an internal Phase-Locked Loop (PLL) that enables the chip to generate its main internal clock frequency from a lower-frequency signal. This reduces emissions and simplifies board design, particularly in systems using low-power CPUs and no external SRAM.
- PM-36 Capabilities
The PM-36 enables the following combinations of operations to be performed on the data stream during one pass through the device: Raster format image data: Converted to Block mode, subsampled 2:1, and JPEG encoded Block format image data: JPEG encoded JPEG-encoded data: JPEG decoded to raw format, upsampled 2:1, and output in Block or Raster format

- Design Considerations
The PM-36 can be easily integrated into a variety of systems. Design features include:
A simple peripheral interface for use with any standard processor Programmable control port bus width (16 or 32 bits) Flexible input and output ports, which simplify system design Input and output ports can be sized at 8, 16, 24, or 32 bits wide and contain bit, byte and word order controls to match any processor bus requirements 256-byte buffer on both input and output ports can minimize or even eliminate external buffering requirements High speed I/O modes, synchronous FIFO and Burst DMA modes The PM-36 requires little in the way of external support chips. A minimal system requires only a frequency source. An external SRAM array (up to 4 MB) may be added to enable raster format data streams. The external SRAM is used to store input or output lines for raster-to-block or block-to-raster conversion operations

* PM-36 Specifications
   Formats Supported
- Grayscale pixels in Raster or Block format (8 bits per pixel)
- Color pixels in Raster or Block format (8 bits per component)
- JPEG-encoded data
- Electrical Specification
- 3.3 Volt power supply
- 5 Volt tolerant I/O (TTL-compatible I/O)
 - Designed and fabricated in 0.35 micron standard cell technology
- Available industry-standard 208 PQFP package with 0.5 mm lead spacing
- Also available in lead-free “green” packaging

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Description
 The ICX419AKB is an interline CCD solid-state image sensor suitable for PAL color video cameras with a diagonal 8mm (Type 1/2) system. Compared with the current product ICX039DNB, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically.

  This chip features a field period readout system and an electronic shutter with variable charge-storage time. Also, this outline is miniaturized by using original package. This chip is compatible with the pins of the ICX039DNB and has the same drive conditions..

Features
• High sensitivity (+6.0dB compared with the ICX039DNB)
• Low smear (–5.0dB compared with the ICX039DNB)
• High D range (+3.0dB compared with the ICX039DNB)
• High S/N
• High resolution and low dark current
• Excellent antiblooming characteristics
• Ye, Cy, Mg, and G complementary color mosaic filters on chip
• Continuous variable-speed shutter
• Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V)
• Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V)
• Horizontal register: 5V drive
• Maximum package dimensions: φ13.2mm

Device Structure
• Interline CCD image sensor
• Optical size: Diagonal 8mm (Type 1/2)
• Number of effective pixels: 752 (H) × 582 (V) approx. 440K pixels
• Total number of pixels: 795 (H) × 596 (V) approx. 470K pixels
• Chip size: 7.40mm (H) × 5.95mm (V)
• Unit cell size: 8.6µm (H) × 8.3µm (V)
• Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels
Vertical (V) direction: Front 12 pixels, rear 2 pixels
• Number of dummy bits: Horizontal 22
Vertical 1 (even fields only)
• Substrate material: Silicon

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• High-Resolution, Solid-State Frame-Transfer Image Sensor
• 17.2-mm Image-Area Diagonal
• 1000 (H) x 1018 (V) Active Elements in Image-Sensing Area
• Square Pixels
• Low Dark Current
• Electron-Hole Recombination Antiblooming
• Dynamic Range . . . More Than 60 dB
• High Sensitivity
• High Photoresponse Uniformity
• High Blue Response
• Single-Phase Clocking
• Solid-State Reliability With No Image Burn-in, Residual Imaging, Image Distortion, Image Lag, or Microphonics

description
 The TC215 is a full-frame charge-coupled-device (CCD) image sensor that provides very high-resolution image acquisition for image-processing applications such as robotic vision, medical X-ray analysis, and metrology. The image format measures 12 mm horizontally by 12.216 mm vertically; the image-area diagonal is 17.2 mm. The image-area pixels are 12-mm square. The image area contains 1018 active lines with 1000 active pixels per line. Six additional dark reference lines give a total of 1024 lines in the image area, and 24 additional dark reference
pixels per line give a total of 1024 pixels per horizontal line.
 The full-frame image sensor should be used with a shutter or with strobed illumination to prevent smearing of the image during readout. To prepare the imaging area for image capture, the photoelectric charge that has accumulated in the image pixels can be transferred into the clearing drain in one millisecond. After image capture (integration time), the readout is accomplished by transferring the charge, one line at a time, into two serial registers, each of which contains 512 data elements and 12 dummy elements. The typical serial-register
clocking rate is 10 megapixels per second. Operating the TC215 at the typical data rate of one field per frame generates video output at a continuous 15 frames per second.
 Gated floating-diffusion detection structures are used with each serial register to convert charge to signal voltage. External reset allows the application of off-chip correlated clamp sample-and-hold amplifiers for low-noise performance. To provide high output-drive capability, both outputs are buffered by low-noise, two-stage, source-follower amplifiers. These two output signals can provide a data rate of 20 megapixels per second when combined off chip. At room temperature, the readout noise is 55 electrons and a minimum dynamic range of 60 dB is available.

SN28846DW TMS3473BDW

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