General Description
The HMC701LP6CE is a SiGe BiCMOS fractional-N frequency synthesizer. The synthesizer includes a 8GHz 16-bit RF N-Divider, a 24-bit delta-sigma modulator, a very low noise digital phase frequency detector (PFD), and a precision controlled charge pump. In addition the synthesizer supports an external step tuned VCO .
The fractional synthesizer features an advanced delta-sigma modulator design that allows ultra-fine frequency step sizes. The synthesizer features the ability to alter both the phase-frequency detector (PFD) gain and the cycle slipping characteristics of the PFD. This feature can reduce the time to arrive at the new frequency by 50% vs. conventional PFDs. Ultra low in-close phase noise also allows wider loop bandwidths for faster frequency hopping.
The synthesizer contains a built-in linear sweeper function, which allows it to perform frequency chirps with a wide variety of sweep times, polarities and dwells, all with an external or automatic sweep trigger.
A General Purpose Output (GPO) bus supports the use of multiple VCO s. In addition the synthesizer has a number of auxiliary clock generation modes that can be accessed via the GPO.

Features
*Fractional or Integer Modes
*8 GHz, 16-Bit RF N-Counter
*24-Bit Step Size Resolution, 3 Hz typ
*Ultra Low Phase Noise 6 GHz, 50 MHz Ref.
-103 / -110 dBc/Hz @ 20 kHz (Frac / Integer)
*Reference Path Input: 200 MHz
*14-Bit Reference Path Divider
*Low Fractional Spurious
*Reference spurs: -90 dBc typ
*Auto and Triggered Sweeper Functions
*Cycle Slip Prevention (CS P) for fast settling
*Autotune support for external step tuned VCO s
*Multi-VCO Support
*Auxiliary Clock Source
*40 Lead 6x6mm SMT Package: 36mm²

Typical Applications
*Base Stations for Mobile Radio (GSM, PCS , DCS , CDMA, WCDMA)
*Wireless LAN s, WiMax
*Communications Test Equipment
*CATV Equipment
*FMCW Sensors
*Automotive Radar
*Phased-Array Systems

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Description
The PE3282A is a dual fractional-N phase-locked loop integrated circuit designed for frequency synthesis and fabricated on Peregrine’s patented UTSi® CMOS process.
Each PLL includes a prescaler, phase detector, charge pump and on-board fractional spur compensation.
The 32/33 RF prescaler (PLL1) operates up to 1.1 GHz and the 16/17 IF prescaler (PLL2) operates up to 510 MHz.
The PE3282A provides fractional-N division with power-of-two denominator values up to 32. This allows comparison frequencies up to 32 times the channel spacing, providing a lower phase-noise floor than integer PLLs.

Features
* Modulo-32 fractional-N main counters
* On-board fractional spur compensation: no tuning required, stable over temperature
* Improved phase noise compared to integer-N architectures
* Low power—8.5 mA at 3 V
* Integrated 1.1 GHz ÷ 32/33 prescaler
* Integrated 510 MHz ÷ 16/17 prescaler

Applications
* Cellular handsets
* Cellular base stations
* Spread-spectrum radio
* Cordless phones
* Pagers

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