The W25X10 (1M-bit), W25X20 (2M-bit), W25X40 (4M-bit) and W25X80 (8M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25X series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code download applications as well as storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and 1μA for power-down. All devices are offered in space-saving packages.
The W25X10/20/40/80 array is organized into 512/1024/2048/4096 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time using the Page Program instruction. Pages can be erased in groups of 16 (sector erase), groups of 256 (block erase) or the entire chip (chip erase). The W25X10/20/40/80 has 32/64/128/256 erasable sectors and 2/4/8/16 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. (See figure 2.)
The W25X10/20/40/80 supports the standard Serial Peripheral Interface (SPI), and a high performance dual output SPI using four pins: Serial Clock, Chip Select, Serial Data I/O and Serial Data Out. SPI clock frequencies of up to 75MHz are supported allowing equivalent clock rates of 150MHz when using the Fast Read Dual Output instruction. These transfer rates are comparable to those of 8 and 16-bit Parallel Flash memories.
A Hold pin, Write Protect pin and programmable write protect, with top or bottom array control features, provide further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification.

*Family of Serial Flash Memories
- W25X10: 1M-bit / 128K-byte (131,072)
- W25X20: 2M-bit / 256K-byte (262,144)
- W25X40: 4M-bit / 512K-byte (524,288)
- W25X80: 8M-bit / 1M-byte (1,048,576)
- 256-bytes per programmable page
- Uniform 4K-byte Sectors / 64K-byte Blocks
*SPI with Single or Dual Outputs
- Clock, Chip Select, Data I/O, Data Out
- Optional Hold function for SPI flexibility
*Data Transfer up to 150M-bits / second
- Clock operation to 75MHz
- Fast Read Dual Output instruction
- Auto-increment Read capability
*Flexible Architecture with 4KB sectors
- Sector Erase (4K-bytes)
- Block Erase (64K-byte)
- Page program up to 256 bytes <2ms
- Up to 100,000 erase/write cycles
- 20-year retention
*Low Power Consumption, Wide Temperature Range
– Single 2.7 to 3.6V supply
- 5mA active current, 1μA Power-down (typ)
- -40° to +85°C operating range
* Software and Hardware Write Protection
- Write-Protect all or portion of memory
- Enable/Disable protection with /WP pin
- Top or bottom array protection
*Space Efficient Packaging
- 8-pin SOIC 150-mil (W25X10/20/40)
- 8-pin SOIC 208-mil (W25X40/80)
- 8-pin PDIP 300-mil (W25X10/20/40/80)
- 8-pin WSON 6x5-mm (W25X10/20/40/80)

W25X20, W25X40, W25X80, W25X10VSNI, W25X20VSNI, W25X40VSNI, W25X80VSNI

댓글을 달아 주세요 Comment

The NAND08GW3C2A and NAND16GW3C2A are multilevel cell (MLC) devices from the NAND Flash 2112-byte page family of non-volatile Flash memories. The NAND08GW3C2A and the NAND16GW3C2A have a density of 8- and 16-Gbit, respectively. The NAND16GW3C2A is composed of two 8-Gbit dice; each die can be accessed independently using two Chip Enable and two Ready/Busy signals. The devices operate from a 3 V VDD power supply.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 10,000 cycles (with ECC on). The device also has hardware security features; a write protect pin is available to give hardware protection against Program and Erase operations.
The devices feature an open-drain, ready/busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor. The memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a time (one in each plane), dividing by two the average program and erase times.
The devices have the Chip Enable “Don’t Care” feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the Read operation.
There is the option of a unique identifier (serial number), which allows the NAND08GW3C2A and the NAND16GW3C2A to be uniquely identified. It is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.
The devices are available in TSOP48 (12 × 20 mm) and LGA52 (12 x 17 x 0.65 mm) packages. To meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are lead-free. In compliance with JEDEC Standard JESD97, the category of second level interconnect is marked on the package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label.
The devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ‘1’.

*High density multilevel cell (MLC) Flash memory
-Up to 16 Gbit memory array
-Up to 512 Mbit spare area
-Cost-effective solutions for mass storage applications
*NAND interface
-x 8 bus width
-Multiplexed address/data
*Supply voltage: VDD = 2.7 to 3.6 V
*Page size: (2048 + 64 spare) bytes
*Block size: (256K + 8K spare) bytes
*Multiplane architecture
-Array split into two independent planes
-Program/erase operations can be performed on both planes at the same time
*Page read/program
-Random access: 60 μs (max)
-Sequential access: 25 ns (min)
-Page program operation time: 800 μs (typ)
*Multipage program time (2 pages): 800 μs (typ)
*Fast block erase
-Block erase time: 2.5 ms (typ)
*Multiblock erase time (2 blocks): 2.5 ms (typ)
*Status register
*Electronic signature
*Serial number option
*Chip enable ‘don’t care’
*Data protection
-Hardware program/erase locked during power transitions
*Development tools
-Error correction code models
-Bad block management and wear leveling algorithm
-HW simulation models
*Data integrity
-10,000 program/erase cycles (with ECC)
-10 years data retention
*ECOPACK® packages available


댓글을 달아 주세요 Comment

General Description
SN11087 is a high-performance integrated circuit to access the NAND type Flash memory via the USB 1.1 bus. It provides a flexible and cost efficient single chip solution for external storage applications such as USB Disk (Flash Disk). With the capability to be pin-to-pin compatible to SN11085, the current user of SN11085 can easily upgrade to SN11087 with no engineering effort needed at all. With all the features inherited from SN11085/086 like the low 6MHz system clock to reduce the EMI, the embedded translation table to eliminate the cost of external memory, the Sonix proprietary randomization algorithm to extend the lifetime of flash memory and ensure the product robustness, and the real time ECC correction function, the SN 11087 adds several other unique features to reduce the cost of the end product and meet the customer’s requirements.
To enrich the product line of the OEM manufacture, with the ability to support 8 pieces of flash memories and the new types of 2G bits flashes, SN11087 can be used to build up a storage device up to 2 Giga bytes. To reduce the total cost of the end product, SN11087 incorporates a power MOS inside to meet the current requirement (500 uA) in USB suspend state. The usage of EEPROM can also now be eliminated by the capability to program the customized vendor/product ID/string in the flash itself. Therefore, the total cost is reduced by upgrade from SN11085 to SN11087.
For fulfilling different customers’ needs, SN11087 now provides several ways to build different end products. The first one is to provide different security functions. The OEM manufacturers can program one of the two ways in manufacturing via software. The flashing ways of LED can also be selected by software now. The pin 35 of SN11087 is now used to support new security feature. The original two security features provided in SN11085/86 still exist. The customers can select any one of them during the mass production stage, making production much easier. With these flexibilities, the manufacturers can easily build different products by using exactly the same components. The only place needs to be changed on PCB is pin 35.
The USB Mass Storage Class compliance capability of SN11087 makes it a truly “plug-and-play” device without vendor drivers under Windows 2000/ME/XP and Mac OS 9/10. SN11087 also provides PC boot up and data security function that exact the same as a floppy disk (1.44M), which makes it an ideal replacement for the legacy floppy disk.

*USB 1.1 12 MHz full-speed compatible
*USB 1.1 Mass Storage Class compliant
*USB Mass Storage Class Bulk-Only Transport 1.0 supported
*USB Mass Storage Class SCSI transparent command set supported
*Low system clock (6MHz) to reduce EMI
*Customized VID, PID, serial number, and 28 characters of Vendor/Product/Revision string supported within flash or external EEPROM.
*EEPROM in system programmable (ISP) capability
*Support Samsung and Toshiba NAND-type flash memory, from 32Mbits to 1Gbits
*Support new type of Samsung NAND type flash memory, from 1Gbits to 4Gbits
*Real-time ECC correction circuit for data integrity and memory access speed acceleration
*Embedded SRAM for logical-to-physical address translation to extend the life time of NAND-type flash
*Support up to 8 NAND type flash memories are supported
*Support up to 2 Gbytes of disk capacity
*Embedded FIFO for upstream and downstream data transfer
*Built-in power MOS to meet USB suspend requirement (500 uA)
*Data transfer rate up to 1.5 MB/s (burst), 1.1 MB/s (read average)
*LED indicator pin
*Three modes of LED flashing patterns can be selected
*Five speed of LED flashing speed provided
*PC boot up capability (host BIOS with USB boot up support is necessary)
*Flash disk security function provided, up to 16 characters of password for high sensitive data protection from illegally access
*Three types of security functions can be selected
*ROM-type flash disk capability provided (permanent write protect)
*No Driver needed under Microsoft Windows ME/2000/XP, Mac OS 9.x/10.x
*Sonix Driver for Microsoft Windows 98
*Sonix mass production tool available for mass production
*Sonix security program available
*Sonix bonus programs available
*Single 3.3V operation
*48 pin LQFP package

댓글을 달아 주세요 Comment

Maxwell Technologies’ 69F1608 high-performance flash memory is a 16M x 8-bit NAND Flash Memory with a spare 128K (131,072) x 8-bit. A program operation programs the 528-byte page in 250 μ s and an erase operation can be performed in 2 ms on an 8K-byte block. Data within a page can be read out at 50 ns cycle time per byte. The on-chip write controller automates all program and erase functions, including pulse repetition, where required, and internal verify and margining of data. Even write-intensive systems can take advantage of the 69F1608’s extended reliability of 1,000,000 program/erase cycles by providing either ECC (Error Correction Code) or real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications. The spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The 69F1608 is an optimum solution for large non-volatile storage applications such as solid state data storage, digital voice recorders, digital still cameras and other applications requiring nonvolatility.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. Capable of surviving in space environments, the 69F1608 is ideal for satellite, spacecraft, and space probe missions. It is available with packaging and screening up to Maxwell Technologies self-defined Class K.

*Single 5.0 V supply
-Memory cell array: (4M + 128k) bit x 8bit
-Data register: (512 + 16) bit x 8bit
-Contains 4 (32 Megabit) Die
*Automatic program and erase
-Page program: (512 + 16) Byte
-Block erase: (8K + 256) Byte
-Status register
*528-Byte page read operation
-Random access: 10 μ s (max)
-Serial page access: 50 ns (min)
*Fast write cycle time
-Program time: 250 μ s (typ)
-Block erase time: 2 ms (typ)
*Command/address/data multiplexed I/O port
*Hardware data protection
-Program/erase lockout during power transitions
*Reliable CMOS floating-gate technology
-Endurance: 1,000,000 program/erase cycles
-Data retention: 10 years
*Command register operation

69F1608RPFK, 69F1608RPFH, 69F1608RPFI, 69F1608RPFE

댓글을 달아 주세요 Comment

The W39L020 is a 2Mbit, 3.3-volt only CMOS flash memory organized as 256K × 8 bits. For flexible erase capability, the 2Mbits of data are divided into 4 uniform sectors of 64 Kbytes, which are composed of 16 smaller even pages with 4 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39L020 results in fast program/erase operations with extremely low current consum ption (compared to other comparable 3.3-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers.

*Single 3.3-volt operations
-3.3-volt Read
-3.3-volt Erase
-3.3-volt Program
*Fast Program operation:
-Byte-by-Byte programming: 50 μS (max.)
*Fast Erase operation:
-Chip Erase cycle time: 100 mS (max.)
-Sector Erase cycle time: 25mS (max.)
-Page Erase cycle time: 25mS (max.)
*Read access time: 70/90 nS
*4 Even sectors with 64K bytes each, which is composed of 16 flexible pages with 4K bytes
*Any individual sector or page can be erased
*Hardware protection:
-Optional 16K byte or 64K byte Top/Bottom Boot Block with lockout protection
*Flexible 4K-page size can be used as Parameter Blocks
*Typical program/erase cycles: 1K/10K
*Twenty-year data retention
*Low power consumption
-Active current: 10 mA (typ.)
-Standby current: 5 μA (typ.)
*End of program detection
-Software method: Toggle bit/Data polling
*TTL compatible I/O
*JEDEC standard byte-wide pinouts
*Available packages: 32L PLCC, 32L TSOP (8 x 20 mm) and 32L STSOP (8 x 14 mm)

W39L020P-70, W39L020P-90, W39L020T-70, W39L020T-90, W39L020Q-70

댓글을 달아 주세요 Comment

The M29W800F is available as known good dice.
Numonyx defines known good dice as standard products offered as dice and tested for functionality and speed. Numonyx's known good die products are as reliable and of the same quality as products delivered in packages.
This datasheet describes the features specific to parts sold as known good dice. It should be read in conjunction with the M29W800F datasheet that detailfully describes the device operation. The M29W800F datasheet is available from the Numonyx website:
The M29W800FB-KGD is a 8-Mbit non-volatile Flash memory that can be erased electrically at the block level and programmed in-system on a single-word basis using a 2.7 V to 3.6 V. On power-up the memory defaults to its read mode where it can be read in the same way as a ROM or EPROM.
The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental program or erase commands from modifying the memory. Program and erase commands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents.
The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards.
The blocks in the memory are asymmetrically arranged. The first or last 64 Kbytes have been divided into four additional blocks. The 16-Kbyte boot block can be used for small initialization code to start the microprocessor, the two 8-Kbyte parameter blocks can be used for parameter storage and the remaining 32-Kbyte is a small main block where the application may be stored.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic.

*Supply voltage
–VCC = 2.7 V to 3.6 V for program, erase and read
*Access times: 90 ns
*Programming time
–10 μs per byte/word typical
*19 memory blocks
-1 boot block (top or bottom location)
–2 parameter and 16 main blocks
*Program/erase controller
– Embedded byte/word program algorithms
*Erase suspend and resume modes
– Read and program another block during erase suspend
*Unlock bypass program command
– Faster production/batch programming
*Temporary block unprotection mode
*Common flash interface
-64-bit security code
*Low power consumption
-Standby and automatic standby
*100,000 program/erase cycles per block
*Electronic signature
-Manufacturer code: 0020h
-Bottom device code M29W800FB: 225Bh


댓글을 달아 주세요 Comment

General Description
The A29L320A is a 32Mbit, 3.3 volt-only Flash memory organized as 2,097,152 words of 16 bits or 4,194,304 bytes of 8 bits each. The 8 bits of data appear on I/O0 - I/O7; the 16 bits of data appear on I/O0~I/O15. The A29L320A is offered in 48-ball TFBGA and 48-Pin TSOP packages. This device is designed to be programmed in-system with the standard system 3.3 volt VCC supply. Additional 12.0 volt VPP is not required for in-system write or erase operations. However, the A29L320A can also be programmed in standard EPROM programmers.
The A29L320A has the first toggle bit, I/O6, which indicates whether an Embedded Program or Erase is in progress, or it is in the Erase Suspend. Besides the I/O6 toggle bit, the A29L320A has a second toggle bit, I/O2, to indicate whether the addressed sector is being selected for erase. The A29L320A also offers the ability to program in the Erase Suspend mode. The standard A29L320A offers access times of 70,80,90 and 120ns, allowing high-speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable ( CE ), write enable (WE ) and output enable (OE ) controls.
The device requires only a single 3.3 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The A29L320A is entirely software command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program command sequence. This initiates the Embedded Program algorithm - an internal algorithm that automatically times the program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase command sequence. This initiates the Embedded Erase algorithm - an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper erase margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
The host system can detect whether a program or erase operation is complete by observing the RY / BY pin, or by reading the I/O7 (Data Polling) and I/O6 (toggle) status bits.
After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The A29L320A is fully erased when shipped from the factory.
The hardware sector protection feature disables operations for both program and erase in any combination of the sectors of memory. This can be achieved via programming equipment.
The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any other sector that is not selected for erasure. True background erase can thus be achieved.
The hardware RESET pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

*Single power supply operation
-Regulated voltage range: 2.7 to 3.6 volt read and write operations for compatibility with high performance 3 volt microprocessors
*Access times:
-70/80/90/120 (max.)
-2mA active read current at 1MHz
-10mA active read current at 5MHz
-20 mA typical program/erase current
-500 nA typical CMOS standby or Automatic Sleep Mode current
*Flexible sector architecture
-Eight 8 Kbyte sectors
-Sixty-three 64 kbyte sectors
-Any combination of sectors can be erased
-Supports full chip erase
-Sector protection:
*Unlock Bypass Program Command
-Reduces overall programming time when issuing multiple program command sequence
*Top or bottom boot block configurations available
*Embedded Algorithms
-Embedded Erase algorithm will automatically erase the entire chip or any combination of designated sectors and verify the erased sectors
-Embedded Program algorithm automatically writes and verifies data at specified addresses
*Typical 100,000 program/erase cycles per sector
*20-year data retention at 125°C
-Reliable operation for the life of the system
*CFI (Common Flash Interface) compliant
-Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices
*Compatible with JEDEC-standards
-Pinout and software compatible with single-power-supply Flash memory standard
-Superior inadvertent write protection
*Data Polling and toggle bits
-Provides a software method of detecting completion of program or erase operations
*Ready / BUSY pin (RY / BY)
-Provides a hardware method of detecting completion of program or erase operations
*Erase Suspend/Erase Resume
-Suspends a sector erase operation to read data from, or program data to, a non-erasing sector, then resumes the erase operation
*Hardware reset pin (RESET )
-Hardware method to reset the device to reading array data
*WP /ACC input pin
-Write protect ( WP ) function allows protection of two outermost boot sectors, regardless of sector protect status
-Acceleration (ACC) function provides accelerated program times
*Hardware/Software temporary sector block unprotect command allows code changes in previously locked sectors
*Hardware/Software sector protect/unprotect command
*Package options
-48-pin TSOP (I) or 48-ball TFBGA
-All Pb-free (Lead-free) products are RoHS compliant

A29L320ATV-70, A29L320ATV-70U, A29L320ATV-70I, A29L320ATV-70F

댓글을 달아 주세요 Comment

The Am27C040 is a 4 Mbit ultraviolet erasable programmable read-only memory. It is organized as 512K bytes, operates from a single +5 V supply, has a static standby mode, and features fast single address location programming. The device is available in windowed ceramic DIP packages and plastic one-time programmable (OTP) packages.
Data can be typically accessed in less than 90 ns, allowing high-performance microprocessors to operate without any WAIT states. The device offers separate Output Enable (OE#) and Chip Enable (CE#) controls, thus eliminating bus contention in a multiple bus microprocessor
AMD’s CMOS process technology provides high speed, low power, and high noise immunity. Typical power consumption is only 100 mW in active mode, and 50 μW in standby mode.
All signals are TTL levels, including programming signals. Bit locations may be programmed singly, in blocks, or at random. The device supports AMD’s Flashrite programming algorithm (100 μs pulses) resulting in typical programming time of 1 minute.

*Fast access time
-Available in speed options as fast as 90 ns
*Low power consumption
-<10 μA typical CMOS standby current
*JEDEC-approved pinout
-Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs
-Easy upgrade from 28-pin JEDEC EPROMs
*Single +5 V power supply
*±10% power supply tolerance standard
*100% Flashrite™ programming
-Typical programming time of 1 minute
*Latch-up protected to 100 mA from –1 V to VCC + 1 V
*High noise immunity
*Compact 32-pin DIP, PDIP, PLCC packages

AM29F400BT-45EC0, AM29F400BB-45EC0, AM29F400BT-45FC0

댓글을 달아 주세요 Comment

General Description
The S70GL01GN00 is a 1024 Mbit, single power supply flash memory device organized as two S29GL512N dies in a single 64-ball Fortified-BGA package. Each S29GL512N die is 512 Mbit, organized as 33,554,432 words or 67,108,864 bytes. The devices have a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers.
Access times as fast as 110 ns is available. Note that each access time has a specific operating voltage range (VCC) and an I/O voltage range (VIO), as specified in the Product Selector Guide‚ on page 5 and the Ordering Information‚ on page 9. The devices are offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE# or CE2#), write enable (WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a VCC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired.
The devices are entirely command set compatible with the JEDEC singlepower-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory.
Device programming and erasure are initiated through command sequences. Once a program or erase operation starts, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four.
Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. Persistent Sector Protection provides in-system, command-enabled protection of any combination of sectors using a single power supply at VCC. Password Sector Protection prevents unauthorized write and erase operations in any combination of sectors through a user-defined 64-bit password.
The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation.
The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device.

Software & Hardware Features
*Software features
- Program Suspend and Resume: read other sectors before programming operation is completed
- Erase Suspend and Resume: read/program other sectors before an erase operation is completed
- Data# polling and toggle bits provide status
- Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
*Hardware features
- Advanced Sector Protection
- WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings
- Hardware reset input (RESET#) resets device
- Ready/Busy# output (RY/BY#) detects program or erase cycle completion

S70GL01GN00FAI010, S70GL01GN00FFI010, S70GL01GN00FAI020 S70GL01GN00FFI020, S70GL01GN00FAI120, S70GL01GN00FFI120 S70GL01GN00FAI012, S70GL01GN00FFI012, S70GL01GN00FAI022
S70GL01GN00FFI022, S70GL01GN00FAI122, S70GL01GN00FFI122
S70GL01GN00FAI013, S70GL01GN00FFI013, S70GL01GN00FAI023 S70GL01GN00FFI023, S70GL01GN00FAI123, S70GL01GN00FFI123

댓글을 달아 주세요 Comment

The A25L016 is 16M bit Serial Flash Memory, with advanced write protection mechanisms,  ccessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 32 blocks, each containing 16 sectors. Each sector is composed of 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 8,192 pages, or 2,097,152 bytes.
The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction, or a sector at a time, using the Sector Erase instruction.

*Family of Serial Flash Memories
- A25L016: 16M-bit /2M-byte
*Flexible Sector Architecture with 4KB sectors
- Sector Erase (4K-bytes) in 60ms (typical)
- Block Erase (64K-bytes) in 0.5s (typical)
*Page Program (up to 256 Bytes) in 0.8ms (typical)
*2.7 to 3.6V Single Supply Voltage
*Dual input / output instructions resulting in an equivalent lock frequency of 200MHz:
- Dual Output Fast Read Instruction
- Dual Input and Output Fast Read Instruction
*SPI Bus Compatible Serial Interface
*100MHz Clock Rate (maximum)
*Deep Power-down Mode 5μA (Max)
*16Mbit Flash memory
- Uniform 4-Kbyte sectors
- Uniform 64-Kbyte blocks
*Electronic Signatures
- JEDEC Standard Two-Byte Signature A25L016: (3015h)
- RES Instruction, One-Byte, Signature, for backward compatibility A25L016 (14h)
*Package options
- 8-pin SOP (209mil), 16-pin SOP (300mil), 8-pin DIP (300mil)
- All Pb-free (Lead-free) products are RoHS compliant

A25L016-F, A25L016-UF, A25L016M-F, A25L016M-UF, A25L016N-F, A25L016N-UF

댓글을 달아 주세요 Comment