DESCRIPTION
The AZ10/100LVEL16 is a differential receiver. The device is functionally equivalent to the E116 device with higher performance capabilities. With output transition times significantly faster than the E116, the LVEL16 is ideally suited for interfacing with high frequency sources.
The LVEL16 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB reference should be connected to one side of the D/D¯ differential input pair. The input signal is then fed to the other D/D¯ input. The VBB pin can support 1.5 mA sink/source current. When used, the VBB pin should be bypassed to ground via a 0.01 μF capacitor.
Under open input conditions internal input clamps will force the Q output LOW.

FEATURES
*Green and RoHS Compliant / Lead (Pb) Free Packages available
*250ps Propagation Delay
*High Bandwidth Output Transitions
*Operating Range of 3.0V to 5.5V
*Internal Input Pulldown Resistors
*Direct Replacement For ON Semiconductor MC10EL16, MC100EL16, & MC100LVEL16
*IBIS Model Files Available on Arizona Microtek Website

AZ10LVEL16D, AZ100LVEL16D, AZ10LVEL16T, AZ100LVEL16T, AZ100LVEL16NG

Trackback :: http://datasheetblog.com/trackback/2880

댓글을 달아 주세요 Comment

GENERAL DESCRIPTION
The ADN4663 is a dual, CMOS, low voltage differential signaling (LVDS) line driver offering data rates of over 600 Mbps (300 MHz), and ultralow power consumption. It features a flow-through pinout for easy PCB layout and separation of input and output signals.
The device accepts low voltage TTL/CMOS logic signals and converts them to a differential current output of typically ±3.1 mA for driving a transmission medium such as a twisted-pair cable. The transmitted signal develops a differential voltage of typically ±355 mV across a termination resistor at the receiving end, and this is converted back to a TTL/CMOS logic level by a line receiver.
The ADN4663 and a companion receiver offer a new solution to high speed point-to-point data transmission, and a low power alternative to emitter-coupled logic (ECL) or positive emitter-coupled logic (PECL).

FEATURES
*±15 kV ESD protection on output pins
*600 Mbps (300 MHz) switching rates
*Flow-through pinout simplifies PCB layout
*300 ps typical differential skew
*700 ps maximum differential skew
*1.5 ns maximum propagation delay
*3.3 V power supply
*±355 mV differential signaling
*Low power dissipation: 23 mW typical
*Interoperable with existing 5 V LVDS receivers
*Conforms to TIA/EIA-644 LVDS standard
*Industrial operating temperature range (−40°C to +85°C)
*Available in surface-mount (SOIC) package

APPLICATIONS
*Backplane data transmission
*Cable data transmission
*Clock distribution

ADN4663BRZ, ADN4663BRZ-REEL7

Trackback :: http://datasheetblog.com/trackback/2684

댓글을 달아 주세요 Comment

GENERAL DESCRIPTION
AM452 is an integrated transducer with an adjustable current output which has been specifically designed for the conditioning of differential input signals. It permits the independent adjustment of the offset and fullscale current using just a few components.
The IC consists of various functional modules. In addition to the instrumentation amplifier in the signal path there is an operational amplifier which is used to set the gain. The offset can be adjusted using the Zero adjust stage and/or the SET stage module.
An additional operational amplifier can supply external components. The adjustable current output stage permits 2- and 3-wire operation by way of a simple amendment to the circuitry.
The IC is distinguished by its many protective functions which include protection against reverse polarity and short-circuiting and also an internal current limit.

FEATURES
*Instrumentation amplifier input with a wide voltage range of ±400mV
*Adjustable gain and offset
*Adjustable current output (e.g. of 0/4...20mA)
*2- and 3-wire operation
*Suitable for HART® applications
*Protection against reverse polarity and short-circuiting
*Output signal limiting
*Integrated current source
*Adjustable integrated reference voltage source of 5 to 10V
*Modular configuration
*Supply voltage of 6...35V
*Temperature range of -40°C...+85°C
*RoHS compliant

TYPICAL APPLICATIONS
Transducers for differential input signals in current output values for:
*Transducers for sensor applications with an internal sensing element supply
*Drivers for the analog industrial power grid (e.g. remote display in current loop operation)
*Differential impedance converters
*Carrier for standard HART® protocol communications
*Modular signal conditioning with digital correction

Trackback :: http://datasheetblog.com/trackback/2304

댓글을 달아 주세요 Comment

GENERAL DESCRIPTION
The ICS85454-01 is a 2:1/1:2 Multiplexer and a member of the HiPerClockSTM family of high performance clock solutions from ICS. The 2:1 Multiplexer allows one of 2 inputs to be selected onto one output pin and the 1:2 MUX switches one input to both of two outputs. This device may be useful for multiplexing multi-rate Ethernet PHYs which have 100Mbit and 1000Mbit transmit/receive pairs onto an optical SFP module which has a single transmit/receive pair. Another mode allows loop back testing and allows the output of a PHY transmit pair to be routed to the PHY input pair. For examples, please refer to the Application Information section of the data sheet.
The ICS85454-01 is optimized for applications requiring very high performance and has a maximum operating frequency in 2.5GHz. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.

FEATURES
*Dual 2:1/1:2 MUX
*Three LVDS outputs
*Three differential inputs
*Differential inputs can accept the following differential levels: LVPECL, LVDS, CML
*Loopback test mode available
*Maximum output frequency: 2.5GHz
*Part-to-part skew: 250ps (maximum)
*Additive phase jitter, RMS: 0.05ps (typical)
*Propagation delay: 550ps (maximum)
*2.5V operating supply
*-40°C to 85°C ambient operating temperature
*Available in both standard and lead-free RoHS compliant packages

ICS85454AK-01, ICS85454AK-01T, ICS85454AK-01LF, ICS85454AK-01LFT

Trackback :: http://datasheetblog.com/trackback/2282

댓글을 달아 주세요 Comment

GENERAL DESCRIPTION
The ICS85408 is a low skew, high performance 1-to-8 Differential-to-LVDS Clock Distribution
Chip and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS85408 CLK, nCLK pair can accept most differential input levels and translates them to 3.3V LVDS output levels. Utilizing Low Voltage Differential Signaling (LVDS), the ICS85408 provides a low power, low noise, low skew, point-to-point solution for distributing LVDS
clock signals.
Guaranteed output and part-to-part skew specifications make the ICS85408 ideal for those applications demanding well defined performance and repeatability.

FEATURES
*8 Differential LVDS outputs
*CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
*Maximum output frequency: 700MHz
*Translates any differential input signal (LVPECL, LVHSTL, SSTL, HCSL) to LVDS levels without external bias networks
*Translates any single-ended input signal to LVDS with resistor bias on nCLK input
*Multiple output enable inputs for disabling unused outputs in reduced fanout applications
*Output skew: 50ps (maximum)
*Part-to-part skew: 550ps (maximum)
*Propagation delay: 2.4ns (maximum)
*3.3V operating supply
*0°C to 70°C ambient operating temperature
*Lead-Free package RoHS compliant

ICS85408BG, ICS85408BGT
ICS85408BGLF, ICS85408BGLFT

Trackback :: http://datasheetblog.com/trackback/2125

댓글을 달아 주세요 Comment

Description
This PLL clock buffer is designed for 2.5 VDD and 2.5 AVDD operation and differential data input and output levels.
This device is a zero-delay buffer that distributes a differential clock input pair (CLKINT, CLKINC) to ten differential pair of clock outputs (YT[0:9], YC[0:9]) and one differential pair feedback clock output (FBOUTT, FBOUTC). The clock outputs are individually controlled by the serial inputs SCLK and SDATA.
The two-line serial bus can set each output clock pair (YT[0:9], YC[0:9]) to the Hi-Z state. When AVDD is grounded, the PLL is turned off and bypassed for test purposes.
The PLL in this device uses the input clocks (CLKINT,CLKINC) and the feedback clocks (FBINT,FBINC) to provide high-performance, low-skew, low-jitter output differential clocks.

Features
*Phase-locked loop clock distribution for Double Data Rate Synchronous DRAM applications
*1:10 differential outputs
*External Feedback pins (FBINT, FBINC) are used to synchronize the outputs to the clock input
*SSCG: Spread Aware™ for EMI reduction
*48-pin SSOP and TSSOP packages
*Conforms to JEDEC JC40 and JC42.5 DDR specifications

CY2SSTV850OC, CY2SSTV850OCT, CY2SSTV850ZC, CY2SSTV850ZCT

Trackback :: http://datasheetblog.com/trackback/1924

댓글을 달아 주세요 Comment

DESCRIPTION
 The AZ10/100ELT20 is a CMOS/TTL to differential PECL translator.
It operates with a single power supply of +3.0 to +5.5 volts, making it ideal for both LVCMOS/LVTTL and CMOS/TTL applications.
The extremely small MLP 8 2x2 mm package makes it ideal for those applications where space, performance and low power are at a premium.
When the D input is left floating, the Q output is forced HIGH, and the Q¯ output is forced LOW. The ELT20 is available in both PECL standards: the AZ10ELT20 is compatible with PECL 10K logic levels while the AZ100ELT20 is compatible with PECL 100K logic levels.

FEATURES
* 0.5ns Typical Propagation Delay
* Differential PECL Outputs
* Flow Through Pinouts
* Operating Range of +3.0V to +5.5V
* Direct Replacement for ON Semi MC10ELT20, MC100ELT20, MC100LVELT20 & Micrel SY89329V
* Available in 2x2 and 3x3 mm MLP Packages
* IBIS Model Files Available on Arizona Microtek Website

AZ100ELT20
AZ100ELT20D
AZ100ELT20DG
AZ100ELT20TG
AZ10/100ELT20XP

Trackback :: http://datasheetblog.com/trackback/1629

댓글을 달아 주세요 Comment

GENERAL DESCRIPTION
 The ICS854054 is a 4:1 Differential-to-LVDS Clock Multiplexer which can operate up to 2.8GHz and is a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS.
The ICS854054 has 4 selectable differential clock inputs. The PCLK, nPCLK input pairs can accept LVPECL, LVDS, CML or SSTL levels.
The fully differential architecture and low propagation delay make it ideal for use in clock distribution circuits.
The select pins have internal pulldown resistors.
The SEL1 pin is the most significant bit and the binary number applied to the select pins will select the same numbered data input (i.e., 00 selects PCLK0, nPCLK0).

FEATURES
* High speed 4:1 differential multiplexer
* One differential LVDS output
* Four selectable differential clock inputs
* PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
* Maximum output frequency: 2.8GHz
* Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx input
* Part-to-part skew: 375ps (maximum)
* Propagation delay: 700ps (maximum)
* Supply voltage range: 3.135V to 3.465V
* -40°C to 85°C ambient operating temperature
* Available in both standard and lead-free RoHS compliant packages

ICS854054AG
ICS854054AGT
ICS854054AGLF
ICS854054AGLFT

Trackback :: http://datasheetblog.com/trackback/1617

댓글을 달아 주세요 Comment