The XCR22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Xilinx offers the XCR22LV10 that offers high speed and low power in a 3V implementation.
The XCR22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.

*Industry's first TotalCMOS™ SPLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and high speed
-Static current of less than 75 μA
-Dynamic current substantially below that of competing devices
-Pin-to-pin delay of only 7.5 ns
*True Zero Power device with no turbo bits or power down schemes
*Function/JEDEC map compatible with Bipolar, UVCMOS, EECMOS 22V10s
*Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP)
-24-pin TSOIC–uses 93% less in-system space than a 28-pin PLCC
-24-pin SOIC
-28-pin PLCC with standard JEDEC pinout
*Available in commercial and industrial operating ranges
*Advanced 0.5μ E2CMOS process
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Varied product term distribution with up to 16 product terms per output for complex functions
*Programmable output polarity
*Synchronous preset/asynchronous reset capability
*Security bit prevents unauthorized access
*Electronic signature for identification
*Design entry and verification using industry standard CAE tools
*Reprogrammable using industry standard device programmers

XCR22V10-10SO24, XCR22V10-7SO24, XCR22V10-10VO24C, XCR22V10-7VO24C

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General Description
Altera FLEX 10KE devices are enhanced versions of FLEX 10K devices.
Based on reconfigurable CMOS SRAM elements, the FLEX architecture incorporates all features necessary to implement common gate array megafunctions.
With up to 200,000 typical gates, FLEX 10KE devices provide the density, speed, and features to integrate entire systems, including multiple 32-bit buses, into a single device.
The ability to reconfigure FLEX 10KE devices enables 100% testing prior to shipment and allows the designer to focus on simulation and design verification.
FLEX 10KE reconfigurability eliminates inventory management for gate array designs and generation of test vectors for fault coverage.
Table 5 shows FLEX 10KE performance for some common designs.
All performance values were obtained with Synopsys DesignWare or LPM functions.
Special design techniques are not required to implement the applications; the designer simply infers or instantiates a function in a Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or chematic design file.

* Embedded programmable logic devices (PLDs), providing system-on-a-programmable-chip (SOPC) integration in a single device
- Enhanced embedded array for implementing megafunctions such as efficient memory and specialized logic functions
- Dual-port capability with up to 16-bit width per embedded array block (EAB)
- Logic array for general logic functions
* High density
- 30,000 to 200,000 typical gates (see Tables 1 and 2)
- Up to 98,304 RAM bits (4,096 bits per EAB), all of which can be used without reducing logic capacity
* System-level features
- MultiVoltTM I/O pins can drive or be driven by 2.5-V, 3.3-V, or 5.0-V devices
- Low power consumption
- Bidirectional I/O performance (tSU and tCO) up to 212 MHz
- Fully compliant with the PCI Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 2.2 for 3.3-V operation at 33 MHz or 66 MHz
- -1 speed grade devices are compliant with PCI Local Bus Specification, Revision 2.2, for 5.0-V operation
- Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic


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General Description
Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer the MultiCore architecture, which combines the strengths of LUT-based and product-term-based devices with an enhanced memory structure.
LUT-based logic provides optimized performance and efficiency for datapath, register-intensive, mathematical, or digital signal processing (DSP) designs.
Product-term-based logic is optimized for complex combinatorial paths, such as complex state machines.
LUT- and productterm-based logic combined with memory functions and a wide variety of MegaCore and AMPP functions make the APEX 20KC architecture uniquely suited for SOPC designs.
Applications historically requiring a combination of LUT-, product-term-, and memory-based devices can now be integrated into one APEX 20KC device.
APEX 20KC devices include additional features such as enhanced I/O standard support, CAM, additional global clocks, and enhanced ClockLock clock circuitry.

* Programmable logic device (PLD) manufactured using a 0.15-μm alllayer copper-metal fabrication process
- 25 to 35% faster design performance than APEXTM 20KE devices
- Pin-compatible with APEX 20KE devices
- High-performance, low-power copper interconnect
- MultiCoreTM architecture integrating look-up table (LUT) logic and embedded memory
- LUT logic used for register-intensive functions
- Embedded system blocks (ESBs) used to implement memory functions, including first-in first-out (FIFO) buffers, dual-port RAM, and content-addressable memory (CAM)
* High-density architecture
- 200,000 to 1 million typical gates (see Table 1)
- Up to 38,400 logic elements (LEs)
- Up to 327,680 RAM bits that can be used without reducing available logic

TAG device, Logic

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Functional Description
 The Cypress PALCE22V10 is a CMOS Flash Erasable second-generation programmable array logic device.
It is implemented with the familiar sum-of-products (AND-OR) logic structure and the programmable macrocell.
The PALCE22V10 is executed in a 24-pin 300-mil molded DIP, a 300-mil cerDIP, a 28-lead square ceramic leadless chip carrier, a 28-lead square plastic leaded chip carrier, and provides up to 22 inputs and 10 outputs.
The PALCE22V10 can be electrically erased and reprogrammed.
The programmable macrocell provides the capability of defining the architecture of each output individually.
Each of the 10 potential outputs may be specified as “registered” or “combinatorial.”
Polarity of each output may also be individually selected, allowing complete flexibility of output configuration.
Further configurability is provided through “array” configurable “output enable” for each potential output.
This feature allows the 10 outputs to be reconfigured as inputs on an individual basis, or alternately used as a combination I/O controlled by the programmable array.
PALCE22V10 features a variable product term architecture.
There are 5 pairs of product term sums beginning at 8 product terms per output and incrementing by 2 to 16 product terms per output.
By providing this variable structure, the PALCE 22V10 is optimized to the configurations found in a majority of applications without creating devices that burden the product term structures with unusable product terms and lower performance.
Additional features of the Cypress PALCE22V10 include a synchronous preset and an asynchronous reset product term.
These product terms are common to all macrocells, eliminating the need to dedicate standard product terms for initialization functions.
The device automatically resets upon power-up.
The PALCE22V10, featuring programmable macrocells and variable product terms, provides a device with the flexibility to implement logic functions in the 500- to 800-gate-array complexity.
Since each of the 10 output pins may be individually configured as inputs on a temporary or permanent basis, functions requiring up to 21 inputs and only a single output and down to 12 inputs and 10 outputs are possible.
The 10 potential outputs are enabled using product terms.
Any output pin may be permanently selected as an output or arbitrarily enabled as an output and an input through the selective use of individual product terms associated with each output.
Each of these outputs is achieved through an individual programmable macrocell.
These macrocells are programmable to provide a combinatorial or registered inverting or non-inverting output.
In a registered mode of operation, the output of the register is fed back into the array, providing current status information to the array.
This information is available for establishing the next result in applications such as control state machines.
In a combinatorial configuration, the combinatorial output or, if the output is disabled, the signal present on the I/O pin is made available to the array.
The flexibility provided by both programmable product term control of the outputs and variable product terms allows a significant gain in functional density through the use of programmable logic.
Along with this increase in functional density, the Cypress PALCE22V10 provides lower-power operation through the use of CMOS technology, and increased testability with Flash reprogrammability.

* Low power
- 90 mA max. commercial (10 ns)
- 130 mA max. commercial (5 ns)
* CMOS Flash EPROM technology for electrical erasability and reprogrammability
* Variable product terms
- 2 x(8 through 16) product terms
* User-programmable macrocell
- Output polarity control
- Individually selectable for registered or combinatorial operation
* Up to 22 input terms and 10 outputs
* DIP, LCC, and PLCC available
- 5 ns commercial version
- 4 ns tCO
- 3 ns tS
- 5 ns tPD
- 181-MHz state machine
- 10 ns military and industrial versions
- 7 ns tCO
- 6 ns tS
- 10 ns tPD
- 110-MHz state machine
- 15-ns commercial, industrial, and military versions
- 25-ns commercial, industrial, and military versions
* High reliability
- Proven Flash EPROM technology
- 100% programming and functional testing


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General Description
 The PEELTM 16CV8 is a Programmable Electrically Erasable Logic (PEEL) device providing an attractive alternative to ordinary PLDs.
The PEELTM 16CV8 offers the performance, flexibility, ease of design and production practicality needed by logic designers today.
The PEELTM 16CV8 is available in 20-pin DIP, PLCC, SOIC and TSSOP packages with 25ns speed and power consumption as low as 37mA.
EE-Reprogrammability provides the convenience of instant reprogramming for development and reusable production inventory minimizing the impact of programming changes or errors. EEReprogrammability also improves factory testability, thus assuring the highest quality possible.
The PEELTM 16CV8 architecture allows it to replace over standard 20- pin PLDs (PAL, GAL, EPLD etc.).
ICT’s PEELTM 16CV8 can be programmed with existing 16CV8 JEDEC file.
Some programmers also allow the PEELTM 16CV8 to be programmed directly from PLD 16L8, 16R4, 16R6 and 16R8 JEDEC files.
Additional development and programming support for the PEELTM16CV8 is provided by popular
third-party programmers and development software.
ICT also offers free PLACE development software.

• Compatible with Popular 16V8 Devices
- 16V8 socket and function compatible
- Programs with standard 16V8 JEDEC file
- 20-pin DIP, SOIC, TSSOP, and PLCC
• CMOS Electrically Erasable Technology
- Superior factory testing
- Reprogrammable in plastic package
- Reduces retrofit and development costs
• Application Versatility
- Replaces random logic
- Super sets standard 20-pin PLDs (PALs)
• Multiple Speed, Power Options
- Speeds range 25ns
- Power as low as 37mA @ 25mHZ
• Development / Programmer Support
- Third party software and programmers
- ICT PLACE Development Software
- Automatic programmer translation and JEDEC file translation software available for the most popular PAL devices


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General Description
 The MAX 7000 family of high-density, high-performance PLDs is based on Altera’s second-generation MAX architecture.
Fabricated with advanced CMOS technology, the EEPROM-based MAX 7000 family provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4 MHz.
MAX 7000S devices in the -5, -6, -7, and -10 speed grades as well as MAX 7000 and MAX 7000E devices in -5, -6, -7, -10P, and -12P speed grades comply with the PCI Special Interest
Group (PCI SIG) PCI Local Bus Specification, Revision 2.2.

* High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture
* 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices
– ISP circuitry compatible with IEEE Std. 1532
* Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices
* Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells
* Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates
* 5-ns pin-to-pin logic delays with up to 175.4-MHz counter frequencies (including interconnect)
* PCI-compliant devices available
* Open-drain output option in MAX 7000S devices
* Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
* Programmable power-saving mode for a reduction of over 50% in each macrocell
* Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
* 44 to 208 pins available in plastic J-lead chip carrier (PLCC), ceramic pin-grid array (PGA), plastic quad flat pack (PQFP), power quad flat pack (RQFP), and 1.0-mm thin quad flat pack (TQFP) packages
* Programmable security bit for protection of proprietary designs
* 3.3-V or 5.0-V operation
– MultiVoltTM I/O interface operation, allowing devices to interface with 3.3-V or 5.0-V devices (MultiVolt I/O operation is not available in 44-pin packages)
– Pin compatible with low-voltage MAX 7000A and MAX 7000B devices
* Enhanced features available in MAX 7000E and MAX 7000S devices
– Six pin- or logic-driven output enable signals
– Two global clock signals with optional inversion
– Enhanced interconnect resources for improved routability
– Fast input setup times provided by a dedicated path from I/O pin to macrocell registers
– Programmable output slew-rate control
* Software design support and automatic place-and-route provided by Altera’s development system for Windows-based PCs and Sun SPARCstation, and HP 9000 Series 700/800 workstations

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* USB-IF Hi-Speed certified to the Universal Serial Bus Specification Rev 2.0
* Interface compliant with the ULPI Specification revision 1.1 in 8-bit mode
* Industry standard UTMI+ Low Pin Interface (ULPI) Converts 54 UTMI+ signals into a standard 12 pin Link controller interface
* 54.7mA Unconfigured Current (typical) - ideal for bus powered applications
* 83uA suspend current (typical) - ideal for battery powered applications
* Latch-Up performance exceeds 150 mA per EIA/JESD 78, Class II
* ESD protection levels of ±8kV HBM without external protection devices
* Integrated protection to withstand IEC61000-4-2 ESD tests (±8kV contact and ±15kV air) per 3rd party test facility
* Supports FS pre-amble for FS hubs with a LS device attached (UTMI+ Level 3)
* Supports HS SOF and LS keep-alive pulse
* Includes full support for the optional On-The-Go (OTG) protocol detailed in the On-The-Go
Supplement Revision 1.0a specification
* Supports the OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
* Allows host to turn VBUS off to conserve battery power in OTG applications
* Supports OTG monitoring of VBUS levels with internal comparators. Includes support for an external VBUS or fault monitor.
* Low Latency Hi-Speed Receiver (43 Hi-Speed clocks Max) allows use of legacy UTMI Links with a ULPI wrapper
* Integrated Pull-up resistor on STP for interface protection allows a reliable Link/PHY start-up with slow Links (software configured for low power)
* Internal 1.8 volt regulators allow operation from a single 3.3 volt supply
* Internal short circuit protection of ID, DP and DM lines to VBUS or ground
* Integrated 24MHz Crystal Oscillator supports either crystal operation or 24MHz external clock input
* Internal PLL for 480MHz Hi-Speed USB operation
* Industrial Operating Temperature -40°C to +85°C
* 32 pin, QFN lead-free RoHS Compliant package (5 x 5 x 0.90 mm height)

The USB3300 is the ideal companion to any ASIC, SoC or FPGA solution designed with a ULPI Hi-Speed USB host, peripheral or OTG core.
The USB3300 is well suited for:
* Cell Phones
* PDAs
* MP3 Players
* Scanners
* External Hard Drives
* Digital Still and Video Cameras
* Portable Media Players
* Printers


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World's first perpendicular magnetic anisotropy MTJ device

Tokyo--Toshiba Corporation today announced important breakthroughs in key technologies for magnetoresistive random access memory (MRAM), a promising, next-generation semiconductor memory device. The company has successfully fabricated a MRAM memory cell integrating the new technologies and verified its stable performance. Full details of the new technologies were presented today at the 52nd Magnetism and Magnetic Materials Conference in Tampa, Florida, USA which is being held from November 5th to 9th.

MRAM is a highly anticipated next-generation non-volatile semiconductor memory device that offers fast random write/access speeds, enhances endurance in operation with very low power consumption. MRAM can theoretically achieve high level integration as the memory cell structure is relatively simple.
In making these major advances, Toshiba applied and proved the spin transfer switching and perpendicular magnetic anisotropy (PMA) technologies in a magnetic tunnel junction, which is a key component in the memory cell.

Spin transfer switching uses the properties of electron spin to invert magnetization and writes data at very low power levels. It is widely regarded as a major candidate among next-generation principles for new memory devices. PMA aligns magnetization in the magnetic layer perpendicularly, either upward or downward, rather than horizontally as in in-plane shape anisotropy layers. The technology is being increasingly used to enhance for storage capacity for high-density hard disc drives (HDDs), and Toshiba has successfully applied it to a semiconductor memory device. With PMA data write operation and magnetic switching can be achieved at a low energy level. Toshiba also overcame the hurdle of achieving the required precision in the interface process and significantly cutting write power consumption.

In order to realize a miniature memory cell based on PMA, Toshiba optimized the materials and device structure of the new MRAM. Close observation of performance confirms stable operation (see the diagram for full explanation of structure).

Toshiba will further enhance development toward establishing fundamental technologies within the coming years.

Development of the new MRAM technologies was partly supported by grants from Japan's New Energy and Industrial Technology Development Organization (NEDO).

Outline of Development

(1) Cell Structure
Cell structure

A material with perpendicular magnetic anisotropy, which is used for recording media and a type of cobalt-iron, is employed in the magnetic layer, with magnesium oxide in the insulating layer and cobalt-iron-boron in the interface layers.

(2) Operational Results
Operational Results

Figure 1
Resistance versus voltage pulses: Shows device resistance characteristics after voltage pulses are applied to perform write operation. The switching between high and low resistive states is clearly seen at the voltage threshold in both the positive and negative directions.
Figure 2
  Resistance versus DC magnetic field: Device resistance characteristics when the magnetic field is applied perpendicular to layers. The high and low resistive states are clearly observed, and are produced by the magnetization direction in the free layer with reference to the reference layer.

(3) Major characteristics and specifications of MRAM device

Major characteristics and specifications of MRAM device

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San Jose, California – January 2, 2008 – Fairchild Semiconductor’s (NYSE: FCS) single-bit, bi-directional translator, FET plus driver module and the industry’s first SD multiplexer were selected as top products in the power and logic categories in the quarterly EETimes and eeProductCenter Ultimate Products Survey.

In the Power category, Fairchild’s FDMF6700, a fully optimized and integrated FET plus driver power stage solution in ultra-compact 6mm x 6mm MLP packaging, ranked four out of ten in technical significance. This product targets space-constrained applications such as small-form-factor desktops, media center PCs, ultra-dense servers, blade servers, advanced gaming systems, graphic cards, networking and telecom equipment and other DC-DC applications.

In the Logic and Programmable Logic category, two of Fairchild’s products were chosen as best of the best, the FXLH1T45 and the FSSD06. The FXLH1T45, a single-bit, bi-directional voltage translator with guaranteed operation from 1.1V to 3.6V, was ranked three out of ten products. This translator offers both uni-directional and bi-directional translation between a variety of voltage levels and provides a needed interface between processors to electronic subsystems. Since this device operates down to 1.1V, it is ideal for the low-power requirements of portable applications. The FSSD06, the industry’s first multiplexer supporting high voltage and dual voltage secure digital (SD)/secure digital I/O (SDIO) and multimedia cards, was ranked nine out of ten in technical significance. Beyond expanding SD/SDIO/MMC capability in multi-functional portable designs, this secure data, two-port multiplexer enables a 1.8V host processor to interface with high-voltage and dual-voltage cards, providing seamless, bi-directional communication while consuming only 1µA of battery power.

The Ultimate Products award is a product peer-review program developed by EE Times and eeProductCenter. Each quarter the editors of eeProductCenter select the ten most significant new products in seven categories, and qualified readers are asked to score the products in terms of technical significance and usability.

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* Available in a 40 ball lead-free RoHS compliant (4 x 4 x 0.9mm) VFBGA package
* Interface compliant with the UTMI specification (60MHz, 8-bit bidirectional interface)
* Only one required power supply (+3.3V)
* Supports 480Mbps Hi-Speed (HS) and 12Mbps Full Speed (FS) serial data transmission rates
* Integrated 45Ω and 1.5kΩ termination resistors reduce external component count
* Internal short circuit protection of DP and DM lines
* On-chip oscillator operates with low cost 24MHz crystal
* Latch-up performance exceeds 150mA per EIA/JESD 78, Class II
* ESD protection levels of 5kV HBM without external protection devices
* SYNC and EOP generation on transmit packets and detection on receive packets
* NRZI encoding and decoding
* Bit stuffing and unstuffing with error detection
* Supports the USB suspend state, HS detection, HS Chirp, Reset and Resume
* Support for all test modes defined in the USB 2.0 specification
* 55mA Unconfigured Current (typical) - ideal for bus powered applications.
* 83uA suspend current (typical) - ideal for battery powered applications.
* Industrial Operating Temperature -40oC to +85oC

The USB3290 is the ideal companion to any ASIC, SoC or FPGA solution designed with a UTMI Hi-Speed USB device (peripheral) core. The USB3290 is well suited for:

* Cell Phones
* MP3 Players
* Scanners
* External Hard Drives
* Digital Still and Video Cameras
* Portable Media Players
* Entertainment Devices
* Printers


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