Description
The Xc4010D and XC4013D are RAM-less, lower-cost versions of the XC4010 and XC4013. They are identical to the XC4010 and XC4013 in all respects, except for the missing on-chip RAM.
The XC4010D and XC4013D are available in most of the same PLCC, PQFP, and PGA packages as their corresponding XC4000 non-D equivalents. See page 2-70 for details.
The XC4010D and XC4013D are also pin-compatible with the XC5210 (see XC5200 Data Sheet for additional information). The XC5210 provides another possible cost-reduction path for lower-performance applications that do not use the XC4000D features like wide-decoders and carry logic.
For complete electrical specifications, see pages 2-47 through 2-55.
For a detailed description of the device features, architecture and configuration methods, see pages 2-9 through 2-45.
For a detailed list of package printouts, please use the cross-referance on page 2-70.
For package physical dimensions and thermal data, see Section 4.

Features
*Third Generation Field-Programmable Gate Array
–Abundant flip-flops
–Flexible function generators
–No on-chip RAM
–Dedicated high-speed carry-propagation circuit
–Wide edge decoders (four per edge)
–Hierarchy of interconnect lines
–Internal 3-state bus capability
–Eight global low-skew clock or signal distribution network
*Flexible Array Architecture
–Programmable logic blocks and I/O blocks
–Programmable interconnects and wide decoders
*Sub-micron CMOS Process
–High-speed logic and Interconnect
–Low power consumption
*Systems-Oriented Features
–IEEE 1149.1-compatible boundary-scan logic support
–Programmable output slew rate (2 modes)
–Programmable input pull-up or pull-down resistors
–12-mA sink current per output
–24-mA sink current per output pair
*Configured by Loading Binary File
–Unlimited reprogrammability
–Six programming modes
*XACT Development System runs on ’386/’486-type PC, Apollo, Sun-4, and Hewlett-Packard 700 series
–Interfaces to popular design environments like Viewlogic, Mentor Graphics and OrCAD
–Fully automatic partitioning, placement and routing
–Interactive design editor for design optimization
–288 macros, 34 hard macros, RAM/ROM compiler

XC4010D, XC4013D
TAG Array, cell, Logic

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DESCRIPTION
CS101 series, a 90 nm standard cell product, is a CMOS ASIC that satisfies user’s demands for lower power consumption and higher speed. The leakage current of the transistors is the minimum level in the industry. Three types of core transistors with a different threshold voltage can be mixed according to user application.
The design rules match industry standards, and a wide range of IP macros are available for use. As well as providing a maximum of 91 million gates, approximately twice the level of integration achieved in previous products, the power consumption per gate is also reduced by about half to 2.7 nW. Also, using the highspeed library increases the speed by a factor of approximately 1.3, with a gate delay time of 12 ps.

FEATURES
*Technology :
- 90 nm Si gate CMOS
- 6- to 10-metal layers.
- Low-K (low permittivity) material is used for all dielectric inter-layers.
- Three different types of core transistors (low leak, standard, and high speed) can be used on the same chip.
- The design rules comply with industry standard processes.
*Power supply voltage : + 0.9 V to + 1.3 V (A wide range is supported.)
*Operation junction temperature : − 40 °C to + 125 °C (standard)
*Gate delay time : tpd = 12 ps (1.2 V, Inverter, F/O = 1)
*Gate power consumption : 2.7 nW/gate (1.2 V, 2 NAND, F/O = 1, operating rate 0.5) , 1.8 nW/gate (1.0 V, 2 NAND, F/O = 1, operating rate 0.5)
*High level of integration : Up to 91 million gates
*Reduced chip sized realized by I/O with pad.
*Two types of library sets are supported. (Performance focused (1.2 V) , Low power consumption supported (0.9 V to 1.3 V) )
*Low power consumption design (multi-power supply design and power gating) is supported.
*Compliance with industry standard design rules enables non-Fujitsu Microelectronics commercial macros to be easily incorporated.
*Compiled cell (RAM, ROM, others)
*Support for ultra high speed (up to 10 Gbps) interface macros.
*Special interfaces (LVDS, SSTL2, others)
*Supports use of industry standard libraries (.LIB).
*Uses industry standard tools and supports the optimum tools for the application.
*Short-term development using a physical prototyping tool
*One pass design using a physical synthesis tool
*Hierarchical design environment for supporting large-scale circuits
*Support for Signal Integrity, EMI noise reduction
*Support for static timing sign-off
*Optimum package range : FBGA, FC-BGA, PBGA,TEBGA

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* Start Up Into a Full Load With Supply Voltages as Low as 0.9 V Over Full Temperature Range
* Minimum 100-mA Output Current From 0.8 V Supply Voltage
* High Power Conversion Efficiency, up to 90%
* Power-Save Mode for Improved Efficiency at Low Output Currents
* Device Quiescent Current less Than 50 uA
* Added System Security With Integrated low-Battery Comparator
* Low-EMI Converter (Integrated Antiringing Switch Across Inductor)
* Micro-Size 10-Pin MSOP Package
* Evaluation Modules Available(TPS6100xEVM-156)
* Applications Include:
   - Single-and Dual-Cell Battery Operated Products
   - MP3-Players and Wireless Headsets
   - Pagers and Cordless Phones
   - Portable Medical Diagnostic Equipment
   - Remote Controls

description
The TPS6100x devices are boost converters intended for systems that are typically operated from a single- or dual-cell nickel-cadmium (NiCd), nickel-metal hydride (NiMH), or alkaline battery. The converter output voltage can be adjusted from 1.5 V to a maximum of 3.3 V and provides a minimum output current of 100 mA. The converter starts up into a full load with a supply voltage of 0.9 V and stays in operation with supply voltages as low as 0.8 V.
 The converter is based on a fixed-frequency, current-mode pulse-width-modulation (PWM) controller that goes into power-save mode at low load currents. The current through the switch is limited to a maximum of 1100 mA, depending on the output voltage. The current sense is integrated to further minimize external component count.
 The converter can be disabled to minimize battery drain when the system is put into standby.
A low-EMI mode is implemented to reduce interference and radiated electromagnetic energy that is caused by the ringing of the inductor when the inductor discharge-current decreases to zero. The device is packaged in the space saving 10-pin MSOP package.

TPS61001 TPS61002 TPS61003 TPS61004 TPS61005 TPS61006 TPS61006
TPS61000DGS TPS61001DGS TPS61002DGS TPS61003DGS TPS61004DGS TPS61005DGS
TPS61006DGS

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GENERAL DESCRIPTION
 The ML4950 is a low power boost regulator designed for low voltage DC to DC conversion in single cell battery powered systems. The maximum switching frequency can exceed 100kHz, allowing the use of small, low cost inductors.
 The combination of integrated synchronous rectification, variable frequency operation, and low supply current make the ML4950 ideal for single cell applications. The ML4950 is capable of start-up with input voltages as low as 1V, and the output voltage can be set anywhere
between 2V and 3V.
 An integrated synchronous rectifier eliminates the need for an external Schottky diode and provides a lower forward voltage drop, resulting in higher conversion efficiency. In addition, low quiescent battery current and variable frequency operation result in high efficiency even at light loads. The ML4950 requires a minimum number of external components and is capable of achieving conversion efficiencies in excess of 90%.
 The circuit also contains a RESET output which goes low when the IC can no longer function due to low input voltage, or when the DETECT input drops below 200mV.

FEATURES
* Guaranteed full load start-up and operation at 1V input
* Pulse Frequency Modulation (PFM) and internal synchronous rectification for high efficiency
* Minimum external components
* Low ON resistance internal switching FETs
* Micropower operation
* Adjustable output voltage (2V to 3V)
* Low battery detect

ML4950CS ML4950ES

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