DESCRIPTION
The MIL-COTS V•I Chip Bus Converter Module is a high efficiency (>95%) Sine Amplitude Converter (SAC) operating from a 240 to 330 Vdc primary bus to deliver an isolated 30 – 41.2 V nominal, unregulated secondary.
The VMB0004MFJ and VMB0004MFT are provided in a V•I Chip package compatible with standard pick-and-place and surface mount assembly processes.

FEATURES
*270 Vdc – 33.75 Vdc 235 W Bus Converter Module
*MIL-STD-704E/F Compliant
*High efficiency (>95%) reduces system power consumption
*High power density (796 W/in3) reduces power system footprint by >40%
*Contains built-in protection features: undervoltage, overvoltage lockout, over current protection, short circuit protection, overtemperature protection.
*Provides enable/disable control, internal temperature monitoring
*Can be paralleled to create multi-kW arrays

TYPICAL APPLICATIONS
*High Voltage 270 V Aircraft Distributed Power
*28 Vdc MIL-COTS PRM Interface (MP028F036M12AL)
*High Density Power Supplies
*Communication Systems

VMB0004MFT

Description
The M25P10-A is a 1 Mbit (128 Kbit x 8) serial Flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.
The memory is organized as 4 sectors, each containing 128 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131,072 bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time, using the Sector Erase instruction.

Features
*1 Mbit of Flash memory
*Page Program (up to 256 bytes) in 1.4 ms (typical)
*Sector Erase (256 Kbit) in 0.65 s (typical)
*Bulk Erase (1 Mbit) in 1.7 s (typical)
*2.3 to 3.6 V single supply voltage
*SPI bus compatible serial interface
*50 MHz Clock rate (maximum)
*Deep Power-down mode 1 μA (typical)
*Electronic signatures
–JEDEC standard two-byte signature (2011h)
–RES instruction, one-byte signature (10h), for backward compatibility
*More than 20 years’ data retention
*Packages
–ECOPACK® (RoHS compliant)

M25P10-AVMN6TP/X, M25P10-AVMP6TP/X, M25P10-AVMB6TP/X

DESCRIPTION
The MA3690/1 chip set has three modes of operation: remote terminal, bus controller, and passive monitor It has a dual bus capability, requires minimum support hardware / software and is implemented on a radiation hard, CMOS/SOS process. For applications requiring access to Terminal Flag, a 48-Pin DIL MA3693 is available as an alternative to the MA3690.
As a remote terminal, the MA3690/1 is fully compatible with Mil-Std-1553B. The chip set obtained SEAFAC approval in December 1987. All options and mode commands specified by the Mil Std are implemented Full and meaningful use is made of status word bits and a comprehensive bit word is provided.
A unique mechanism has been incorporated that allows the subsystem to declare illegal commands legal, and vice versa, before the chip set services the command. It should be noted that use of this mechanism is optional and that the system defaults to normal operation if the option is not required. The chip set is easily interfaced to subsystem memory and is sufficiently flexible to ensure compatibility with a wide range of microprocessors.
As a bus controller the MA3690/1 has the ability to initiate all types of 1553B transfer on either of the two buses An instruction word is set up by the subsystem, prior to transmission, which contains details of transfer type and bus selection. Four bits of the instruction word have been used to specify the conditions under which the chip set will generate a subsystem interrupt. The most significant bits of the instruction word have been used to specify the conditions under which the chip set will perform an automatic retry and the number of retries to be carried out (max. 3). At the end of each instruction execution cycle, the chip set writes a report word into the subsystem memory; the contents of which give the subsystem an indication of the degree of success of the transfer.
The bus controller may be used in either of two configurations, i.e. single shot or table driven.
In the single shot configuration, the controller is under direct control from the subsystem (processor). In table driven configuration, the controller is given greater autonomy to execute a table of instructions held in either ROM or RAM.
As a passive monitor, the chip set will monitor all bus activity and pass any associated information to the subsystem. As the name implies, in this mode of operation, the chip set is truly passive and will not reply to command instructions.

FEATURES
*Radiation Hard to 1MRads (Si)
*High SEU Immunity, Latch-Up Free
*CMOS-SOS Technology
*All Inputs and Outputs Fully TTL or CMOS Compatible
*Military Temperature Range -55 to +125°C
*Dual Bus Capability
*Minimal Subsystem Interface
*Powerful Bus Control Facility
*Complete Remote Terminal Protocol
*SEAFAC Approved

MA3691, MA3693, MAS3690CL, MAR3690CL, MAS3691CLMAR3691CL

DESCRIPTION
Maxwell Technologies’ 54LVTH162245 devices are 16-bit (dual-octal) non-inverting 3-state transceivers designed for low-voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. The devices allow data transmission from the A bus to the B bus or form the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output enable (OE) input can be used to disable the device so that the buses are effectively isolated. The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ωseries resistors to reduce overshoot and undershoot.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S.

FEATURES
*A-Port outputs have equivalent 22-Ω series resistors, so no external resistors are required
*Support mixed-mode signal operation (5V input and output voltages with 3.3V VCC)
*Support unregulated battery operation down to 2.7V
*TypicalVOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
*IOFF and power-up 3-state support hot insertion
*Bus hold on data inputs eliminates the need for external pullup/pulldown resistors
*Distributed VCC and GND pin configuration minimizes highspeed switching noise
*Flow-through architecture optimizes PCB layout
*Total dose hardness:
-100 krad (Si), depending upon space mission
*Package: 48 pin RAD-PAK® flat pack

54LVTH162245RPFS, 54LVTH162245RPFB, 54LVTH162245RPFE

Description
The M25PE20 and M25PE10 are 2 Mbit (256 Kb × 8 bit) and 1 Mbit (128 Kb × 8 bit) serial paged Flash memories, respectively.
They are accessed by a high speed SPI-compatible bus.
The memories can be written or programmed 1 to 256 bytes at a time, using the Page Write or Page Program instruction.
The Page Write instruction consists of an integrated Page Erase cycle followed by a Page Program cycle.
The M25PE20 memory is organized as 4 sectors, each containing 256 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 1024 pages, or 262,144 bytes.
The M25PE10 memory is organized as 2 sectors, each containing 256 pages.
Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 512 pages, or 131, 072 bytes.
The memories can be erased a page at a time, using the Page Erase instruction, a subsector at a time, using the SubSector Erase instruction, a sector at a time, using the Sector Erase instruction or as a whole, using the Bulk Erase instruction.
The memory can be write protected by either hardware or software using a mix of volatile and non-volatile protection features, depending on the application needs.
The protection granularity is of 64 Kbytes (sector granularity).

Features
* 1 or 2 Mbit of page-erasable Flash memory
* 2.7 V to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 75 MHz clock rate (maximum)
* Page size: 256 bytes
- Page Write in 11 ms (typical)
- Page Program in 0.8 ms (typical)
- Page Erase in 10 ms (typical)
* SubSector Erase (32 Kbits)
* Sector Erase (512 Kbits)
* Bulk Erase (1 Mbit for M25PE10, 2 Mbits for M25PE20)
* Deep Power-down mode 1 μA (typical)
* Electronic signature
- JEDEC standard two-byte signature
(8012h for M25PE20, 8011h for M25PE10)
- Unique ID code (UID) with 16 bytes readonly, available upon customer request only in the T9HX process
* Software write protection on a 64-Kbyte sector basis
* More than 100 000 Write cycles
* More than 20 years data retention
* Hardware write protection of the memory area selected using the BP0 and BP1 bits
* Package
- ECOPACK® (RoHS compliant)

M25PE10
M25PE20-VMN6TP
M25PE20-VMP6TP

Description
The Si9243EY is a monolithic bus transceiver designed to provide bidirectional serial communication in automotive diagnostic applications.
The device incorporates protection against overvoltages and short circuits to GND or VB.
The transceiver pin is protected and can be driven beyond the VBAT voltage.
The Si9243EY contains temperature and short circuit fault detection circuits.
In the transmit mode, load shorts and opens are generally detected by the processor
monitoring RXK and TX.
When the two mirror each other there is no fault, but the Si9243EY will turn off the K output in the event of over temperature or short circuit to VBAT to protect the IC.
The fault will be reset when TX toggles “high.”
TX is set “high” for receive only.
The RX output is capable of driving CMOS or 1 X LSTTL load.
The Si9243EY is built on the Siliconix BiC/DMOS process.
This process supports bipolar transistors, CMOS, and DMOS. An epitaxial layer prevents latchup.
The Si9243EY is available in a 8-pin SO package and operates over the automotive temperature range (–40 to 125C).

Features
* Single-Ended Transceiver
* Survives Shorts and Transients on Automotive Bus
* Wide Power Supply Voltage Range
* Fault Detection
* ISO 9141 Compatible

Description
The M25P05-A is a 512-Kbit (64 Kbits ×8) serial flash memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the page program instruction.
The memory is organized as 2 sectors, each containing 128 pages.
Each page is 256 bytes wide.
Thus, the whole memory can be viewed as consisting of 256 pages, or 65,536 bytes.
The whole memory can be erased using the bulk erase instruction, or a sector at a time, using the sector erase instruction.

Features
* 512 Kbits of flash memory
* Page program (up to 256 bytes) in 1.4 ms (typical)
* Sector erase (256 Kbits) in 0.65 s (typical)
* Bulk erase (512 Kbits) in 0.85 s (typical)
* 2.3 to 3.6 V single supply voltage
* SPI bus compatible serial interface
* 50 MHz clock rate (maximum)
* Deep power-down mode 1 μA (typical)
* Electronic signatures
- JEDEC standard two-byte signature (2010h)
- RES instruction, one-byte, signature (05h), for backward compatibility
* More than 100,000 erase/program cycles per sector
* More than 20 years data retention
* ECOPACK® packages available

Description
Fairchild switch FST3125 provides four high-speed CMOS TTL-compatible bus switches.
The low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise.
The device is organized as four one1-bit switches with separate /OE inputs.
When /OE is LOW, the switch is ON and port A is connected to port B.
When /OE is HIGH, the switch is OPEN and a high-impedance state exists between the two ports.

Features
* 4Ω Switch Connection between Two Ports
* Minimal Propagation Delay through the Switch
* Low ICC
* Zero Bounce in Flow-through Mode
* Control Inputs Compatible with TTL Level

FST3125M
FST3125MX
FST3125QSC
FST3125QSCX
FST3125MTC
FST3125MTCX

DESCRIPTION
 This 1-bit to 4-bit address driver is built using advanced dual metal CMOS technology.
The ALVCH162344 device is used in applications in which four separate memory locations must be addressed by a single address.
The ALVCH162344 has series resistors in the device output structure which will significantly reduce line noise when used with light loads.
This driver has been designed to drive ±12mA at the designated threshold levels.
The ALVCH162344 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high-impedance.
This prevents floating inputs and eliminates the need for pull-up/down resistors.

FEATURES
* 0.5 MICRON CMOS Technology
* Typical tSK(o) (Output Skew) < 250ps
* ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
* VCC = 3.3V ± 0.3V, Normal Range
* VCC = 2.7V to 3.6V, Extended Range
* VCC = 2.5V ± 0.2V
* CMOS power levels (0.4μ W typ. static)
* Rail-to-Rail output swing for increased noise margin
* Available in SSOP, TSSOP, and TVSOP packages

APPLICATIONS
* 3.3V high speed systems
* 3.3V and lower voltage computing systems

DRIVE FEATURES
* Balanced Output Drivers: ±12mA
* Low switching noise

IDT74ALVCH162344PV
IDT74ALVCH162344PA
IDT74ALVCH162344PF

General description
 The 74AHC/AHCT245 is a high-speed Si-gate CMOS device.
The 74AHC/AHCT245 is an octal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions.
The 74AHC245/74AHCT245 features an Output Enable (OE) input for easy cascading and a send/receive (DIR) input for direction control.
OE controls the outputs so that the buses are effectively isolated.

Features
* Balanced propagation delays
* All inputs have a Schmitt-trigger action
* Inputs accepts voltages higher than VCC
* For 74AHC245 only: operates with CMOS input levels
* For 74AHCT245 only: operates with TTL input levels
* ESD protection:
* HBM JESD22-A114E exceeds 2000 V
* MM JESD22-A115-A exceeds 200 V
* CDM JESD22-C101C exceeds 1000 V
* Multiple package options
* Specified from -40 °C to +85 °C and from -40 °C to +125 °C

74AHCT245D
74AHCT245PW
74AHCT245BQ