'buffered' related articles 2

  1. 2008/06/07 AAT4901 - Buffered Power Full-Bridge
  2. 2008/05/02 EBE51FD8AGFD - 512MB Fully Buffered DIMM

General Description
 The AAT4901 FastSwitch™ is a member of AnalogicTech’s Application Specific Power MOSFET™ (ASPM™) product family.
It is a full-bridge buffered power stage operating with an input voltage range of 2.0V to 5.5V. The device is designed to operate with a switching frequency of up to 2MHz, minimizing the cost and size of external components.
The AAT4901 is protected from shoot-through current by integrated break-before-make circuitry. The drivers can be independently controlled and their propagation delay, from input to output, is typically between 8ns-19ns dependent upon logic option.
Four options are offered providing a single input control, dual input control or as two independent half-bridges.
Other features include low RDS(ON) and low quiescent current allowing for high efficiency performance.
The AAT4901 is available in the space-saving, Pb-free 8-pin SC70JW package and is rated over the -40°C to +85°C temperature range.

* VIN Range: 2.0V–5.5V
* RDS(ON):
- High-side 220mΩ
- Low-side 160mΩ
* Break-Before-Make Shoot–Through Protection
* 4 Options
- Single Control Input with Enable
* Two Logic Versions
- Dual Control Input with Brake Function
- Dual Half-bridge
* Low Quiescent Current:
- 10μA (max) DC
- 4mA (max) at 1MHz
* -40°C to +85°C Temperature Range
* SC70JW-8 Package

- DC Motor Drive
- Door Locks
- Dual Low-Side MOSFET Gate Driver
- Fan Motors
- High Frequency DC/DC Converters
- High Speed Line Drive
- Proximity Detectors


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* Density: 512MB
* Organization
- 64M words × 72 bits, 1 rank
* Mounting 9 pieces of 512M bits DDR2 SDRAM sealed in FBGA
* Package
- 240-pin fully buffered, socket type dual in line memory module (FB-DIMM)
  PCB height: 30.35mm
  Lead pitch: 1.00mm
- Advanced Memory Buffer (AMB): 655-ball FCBGA
- Lead-free (RoHS compliant)
* Power supply
- DDR2 SDRAM: VDD = 1.8V ± 0.1V
- AMB: VCC = 1.5V + 0.075V/−0.045
* Data rate: 667Mbps/533Mbps (max.)
* Four internal banks for concurrent operation (components)
* Interface: SSTL_18
* Burst lengths (BL): 4, 8
* /CAS Latency (CL): 3, 4, 5
* Precharge: auto precharge option for each burst access
* Refresh: auto-refresh, self-refresh
* Refresh cycles: 8192 cycles/64ms
- Average refresh period
  7.8μs at 0°C ≤ TC ≤ +85°C
  3.9μs at +85°C < TC ≤ +95°C
* Operating case temperature range
- TC = 0°C to +95°C

* JEDEC standard Raw Card A Design
* Industry Standard Advanced Memory Buffer (AMB)
* High-speed differential point-to-point link interface at 1.5V (JEDEC draft spec)
- 14 north-bound (NB) high speed serial lanes
- 10 south-bound (SB) high speed serial lanes
* Various features/modes:
- MemBIST and IBIST test functions
- Transparent mode and direct access mode for DRAM testing
- Interface for a thermal sensor and status indicator
* Channel error detection and reporting
* Automatic DDR2 SDRAM bus and channel calibration
* SPD (serial presence detect) with 1piece of 256 byte serial EEPROM


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