• Density: 512M bits
• Organization
- 16M words × 8 bits × 4 banks (EDE5108AJBG)
- 8M words × 16 bits × 4 banks (EDE5116AJBG)
• Package
- 60-ball FBGA (EDE5108AJBG)
- 84-ball FBGA (EDE5116AJBG)
- Lead-free (RoHS compliant)
• Power supply: VDD, VDDQ = 1.8V ± 0.1V
• Data rate: 800Mbps/667Mbps (max.)
• 1KB page size (EDE5108AJBG)
- Row address: A0 to A13
- Column address: A0 to A9
• 2KB page size (EDE5116AJBG)
- Row address: A0 to A12
- Column address: A0 to A9
• Four internal banks for concurrent operation
• Interface: SSTL_18
• Burst lengths (BL): 4, 8
• Burst type (BT):
- Sequential (4, 8)
- Interleave (4, 8)
• /CAS Latency (CL): 3, 4, 5, 6
• Precharge: auto precharge option for each burst access
• Driver strength: normal/weak
• Refresh: auto-refresh, self-refresh
• Refresh cycles: 8192 cycles/64ms
- Average refresh period
7.8μs at 0°C ≤ TC ≤ +85°C
3.9μs at +85°C < TC ≤ +95°C
• Operating case temperature range
- TC = 0°C to +95°C

• Double-data-rate architecture; two data transfers per clock cycle
• The high-speed data transfer is realized by the 4 bits prefetch pipelined architecture
• Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the receiver
• DQS is edge-aligned with data for READs; centeraligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK transitions
• Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
• Data mask (DM) for write data
• Posted /CAS by programmable additive latency for better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die- Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8 organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended Data Strobe operation



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· Member of the Texas Instruments Widebus+™ Family
· TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
· OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
· Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
· LVTTL Interfaces Are 5-V Tolerant
· Medium-Drive GTLP Outputs (50 mA)
· LVTTL Outputs (–24 mA/24 mA)
· GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
· Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
· Bus Hold on A-Port Data Inputs
· Distributed VCC and GND Pins Minimize High-Speed Switching Noise
· Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

The SN74GTLPH32945 is a medium-drive, 32-bit bus transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It is partitioned as four 8-bit transceivers. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC circuitry,
and TI-OPC circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 W.
GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3.
The ac specification of the SN74GTLPH32945 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.
Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.
This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.
This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.
Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.


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• High Performance, Low Power AVR®32 UC 32-Bit Microcontroller
– Compact Single-cycle RISC Instruction Set Including DSP Instruction Set
– Read-Modify-Write Instructions and Atomic Bit Manipulation
– Up to 66 MHz Clock Frequency with 1.24 DMIPS/MHz
– Memory Protection Unit
• Multi-hierarchy Bus System
– High-Performance Data Transfers on Separate Buses for Increased Performance
– 15 Peripheral DMA Channels for Automatic Data Transfer
• Internal High-Speed Flash
– 512K Bytes, 256K Bytes, 128K Bytes Versions
– Single Cycle Access up to 30 MHz
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed
– 1ms Page Programming Time and 2ms Full-Chip Erase Time
– 100,000 Write Cycles, 10-year Data Retention Capability
– Flash Security Locks and User Defined Configuration Area
• Internal High-Speed SRAM, Single-Cycle Access at Full Speed
– 64K Bytes (512KB and 256KB Flash), 32K Bytes (128KB Flash)
• External Memory Interface on AT32UC3A0 Derivatives
– SDRAM / SRAM Compatible Memory Bus (16-bit Data and 24-bit Address Buses)
• Interrupt Controller
– Autovectored Low Latency Interrupt Service with Programmable Priority
• System Functions
– Power and Clock Manager Including Internal RC Clock and One 32KHz Oscillator
– Two Multipurpose Oscillators and Two Phase-Lock-Loop (PLL)
– Watchdog Timer, Real-Time Clock Timer
• Universal Serial Bus (USB)
– Device 2.0 Full Speed and On-The-Go (OTG) Low Speed and Full Speed
– Flexible End-Point Configuration and Management with Dedicated DMA Channels
– On-chip Transceivers Including Pull-Ups
• Ethernet MAC 10/100 Mbps interface
– 802.3 Ethernet Media Access Controller
– Supports Media Independent Interface (MII) and Reduced MII (RMII)
• One Three-Channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, PWM, Capture and Various Counting Capabilities
• One 7-Channel 16-bit Pulse Width Modulation Controller (PWM)
• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
– Independant Baudrate Generator, Support for IrDA and ISO7816 interfaces
– Support for Hardware Handshaking, RS485 Interfaces and Modem Line
• Two Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals
• One Synchronous Serial Protocol Controller
– Supports I2S and Generic Frame-Based Protocols
• One Master/Slave Two-Wire Interface (TWI), 400kbit/s I2C-compatible
• One 8-channel 10-bit Analog-To-Digital Converter
• On-Chip Debug System (JTAG interface)
– Nexus Class 2+, Runtime Control, Non-Intrusive Data and Program Trace
• 100-pin TQFP (69 GPIO pins), 144-pin LQFP (109 GPIO pins)
• 5V Input Tolerant I/Os
• Single 3.3V Power Supply

 The AT32UC3A is a complete System-On-Chip microcontroller based on the AVR32 UC RISC
processor running at frequencies up to 66 MHz. AVR32 UC is a high-performance 32-bit RISC
microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density and high performance.

 The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems. Higher
computation capabilities are achievable using a rich set of DSP instructions.
The AT32UC3A incorporates on-chip Flash and SRAM memories for secure and fast access.
For applications requiring additional memory, an external memory interface is provided on
AT32UC3A0 derivatives.

 The Peripheral Direct Memory Access controller enables data transfers between peripherals and memories without processor involvement. PDCA drastically reduces processing overhead when transferring continuous and large data streams between modules within the MCU.
The PowerManager improves design flexibility and security: the on-chip Brown-Out Detector
monitors the power supply, the CPU runs from the on-chip RC oscillator or from one of external
oscillator sources, a Real-Time Clock and its associated timer keeps track of the time.
The Timer/Counter includes three identical 16-bit timer/counter channels. Each channel can be
independently programmed to perform frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation.

 The PWM modules provides seven independent channels with many configuration options
including polarity, edge alignment and waveform non overlap control. One PWM channel can
trigger ADC conversions for more accurate close loop control implementations.
The AT32UC3A also features many communication interfaces for communication intensive
applications. In addition to standard serial interfaces like UART, SPI or TWI, other interfaces like
flexible Synchronous Serial Controller, USB and Ethernet MAC are available.
The Synchronous Serial Controller provides easy access to serial communication protocols and audio standards like I2S.

 The Full-Speed USB 2.0 Device interface supports several USB Classes at the same time
thanks to the rich End-Point configuration. The On-The-GO (OTG) Host interface allows device
like a USB Flash disk or a USB printer to be directly connected to the processor.
The media-independent interface (MII) and reduced MII (RMII) 10/100 Ethernet MAC module
provides on-chip solutions for network-connected devices.
AT32UC3A integrates a class 2+ Nexus 2.0 On-Chip Debug (OCD) System, with non-intrusive
real-time trace, full-speed read/write memory access in addition to basic runtime control.


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The MB89890 series is a line of single-chip microcontrollers containing a great variety of peripheral functions such as dual clock control systems, 4-stage operating speed controller, DTMF signal generator, timer, PWM timer, serial interface, modem, A/D converter and external interrupt, as well as compact instruction set.

• F2MC-8L family CPU core
• Dual clock control system
• Maximum memory size: 64 Kbytes
• Minimum execution time: 0.5 ms at 8 MHz
• Interrupt processing time: 4.5 ms at 8 MHz
• I/O ports: Max 85 ports
• 21-bit time-base counter
• 8-bit PWM timer
• DTMF generator
• 8/16-bit timer
• 8-bit serial I/O
• Serial I/O with 1-byte buffer
• A/D converter
• Modem timer (pulse-width counter)
• Modem signal output
• External interrupt: 16 channels
• Power-on reset function
• Low-power consumption modes (subclock mode, watch mode, sleep mode, stop mode)
• CMOS technology

MB89899 MB89P899 MB89PV890 MB89898

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General Description
 The EM78P468N/L is an 8-bit microprocessor designed and developed with low-power and high-speed CMOS technology. Integrated onto a single chip are on chip Watchdog Timer (WDT), Data RAM, ROM, programmable real time clock counter, internal/external interrupt, power down mode, LCD driver, infrared transmitter function, and tri-state I/O.

 The series has an on-chip 4K×13-bit Electrical One Time Programmable Read Only Memory (OTP-ROM). The EM78P468L provides multi-protection bits to prevent intrusion of user’s OTP memory code. Seven Code option bits are available to meet user’s requirements. Special 13 bits customer ID options are provided as well.
 With its enhanced OTP-ROM feature, the EM78P468N/L provides a convenient way of developing and verifying user’s programs. Moreover, this OTP device offers the advantages of easy and effective program updates, using development and programming tools. User can avail of the ELAN Writer to easily program his development code.

* CPU Configuration
• 4K×13 bits on-chip OTP-ROM
• 144 bytes general purpose register
• 128 bytes on-chip data RAM
• 272 bytes SRAM
• 8 level stacks for subroutine nesting
• Power-on voltage detector provided (2.0±0.1V) for EM78P468N
• Power-on voltage detector provided (1.7±0.1V) for EM78P468L
* I/O Port Configuration
• Typically, 12 bi-directional tri-state I/O ports.
• 16 bi-directional tri-state I/O ports shared with LCD segment output pin.
• Up to 28 bi-directional tri-state I/O ports
* Operating Voltage and Temperature Range:
- EM78P468N
• Commercial: 2.3V ~ 5.5 V. (at 0°C~+70°C)
• Industrial: 2.5V ~ 5.5 V. (at -40°C ~+85°C)
- EM78P468L
• Commercial: 2.1 V ~ 5.5 V. (at 0°C ~+70°C)
• Industrial: 2.3V ~ 5.5 V. (at -40°C ~+85°C)
* Operating Mode:
• Normal mode: The CPU is operated on main oscillator frequency (Fm)
• Green mode: The CPU is operated on sub-oscillator frequency (Fs) and main oscillator (Fm) is stopped
• Idle mode: CPU idle, LCD display remains working
• Sleep mode: The whole chip stops working
♦ Input port wake-up function (Port 6, Port 8). Works on Idle and Sleep mode.
♦ Operation speed: DC ~ 10MHz clock input
♦ Dual clock operation
*  Oscillation Mode
• High frequency oscillator can select among Crystal, RC, or PLL (phase lock loop)
• Low frequency oscillator can select between Crystal or RC mode
* Peripheral Configuration
• 8-bit real time clock/counter (TCC)
• One infrared transmitter / PWM generator function
• Four sets of 8 bits auto reload down-count timer can be used as interrupt sources
♦ Counter 1: independent down-count timer
♦ Counter 2, High Pulse Width Timer (HPWT), and Low Pulse Width Timer (LPWT) shared with IR function.
♦ Programmable free running on chip watchdog timer (WDT). This function can operate on Normal, Green and Idle mode.
* Eight Interrupt Sources: Three External and Five Internal
• Internal interrupt source: TCC; Counters 1, 2; High/Low pulse width timer.
• External interrupt source : INT0, INT1 and Pin change wake-up (Port 6 and Port 8)
* LCD Circuit
• Common driver pins: 4
• Segment driver pins: 32
• LCD Bias: 1/3, 1/2 bias
• LCD Duty: 1/4, 1/3, 1/2 duty
* Package Type:
• Dice form: 59 pins
• QFP-64 pin: EM78P468NQxS/xJ (Body 14mm × 20mm)
• LQFP-64 pin: EM78P468NAQxS/xJ (Body 7mm × 7mm)
• LQFP-44 pin: EM78P468NBQxS/xJ (Body 10mm × 10mm)
• QFP-44 pin: EM78P468NCQxS/xJ (Body 10mm × 10mm)
Note: Green products do not contain hazardous substances


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General Description
NOTE: This is Advance Information for products currently in development. ALL specifications are design targets and are subject to change.

 The ADC14C065, ADC14C080, ADC14C095, and ADC14105 are high-performance CMOS analog-to-digital converters capable of converting analog input signals into 14-bit digital words at rates up to 65/80/95/105 Mega Samples Per Second (MSPS) respectively. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance.
A  unique sample-and-hold stage yields a full-power bandwidth of 1GHz. The ADC14C065/080/095/105 may be operated from a single +3.3V power supply and consumes low power.

 A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C065/080/095/105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2’s complement) and duty cycle
stabilizer are pin-selectable.
 The duty cycle stabilizer maintains performance over a wide range of clock duty cycles.
The ADC14C065/080/095/105 is available in a 32-lead LLP package and operates over the industrial temperature range

*1 GHz Full Power Bandwidth
* Internal sample-and-hold circuit
* Low power consumption
* Internal precision reference
* Data Ready output clock
* Clock Duty Cycle Stabilizer
* Single +3.3V supply operation
* Power-down mode
* Offset binary or 2’s complement output data format
* 32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch)

Key Specifications
* For ADC14C105
* Resolution 14 Bits
* Conversion Rate 105 MSPS SNR (fIN = 240 MHz) 72 dBFS (typ)
* SFDR (fIN = 240 MHz) 83 dBFS (typ)
* Full Power Bandwidth 1 GHz (typ)
* Power Consumption 400 mW (typ)

* High IF Sampling Receivers
* Wireless Base Station Receivers
* Test and Measurement Equipment
*Communications Instrumentation
*Portable Instrumentation
TAG bit, Converter

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• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 1K Byte In-System Programmable Flash Program Memory
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program Data Security
• Peripheral Features
– Interrupt and Wake-up on Pin Change
– Two 8-bit Timer/Counters with Separate Prescalers
– One 150 kHz, 8-bit High-speed PWM Output
– 4-channel 10-bit ADC
One Differential Voltage Input with Optional Gain of 20x
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
• Special Microcontroller Features
– In-System Programmable via SPI Port
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal, Calibrated 1.6 MHz Tunable Oscillator
– Internal 25.6 MHz Clock Generator for Timer/Counter
– External and Internal Interrupt Sources
– Low-power Idle and Power-down Modes
• Power Consumption at 1.6 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down: < 1 µA
• I/O and Packages
– 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V
• Internal 1.6 MHz System Clock

The ATtiny15L is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny15L achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

 The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.

 The ATtiny15L provides 1K byte of Flash, 64 bytes EEPROM, six general purpose I/O
lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with highspeed
PWM output, internal Oscillators, internal and external interrupts, programmable
Watchdog Timer, 4-channel 10-bit Analog-to-Digital Converter with one differential voltage
input with optional 20x gain, and three software-selectable Power-saving modes.

 The Idle mode stops the CPU while allowing the ADC, anAlog Comparator, Timer/Counters and interrupt system to continue functioning. The ADC Noise Reduction mode facilitates high-accuracy ADC measurements by stopping the CPU while allowing the ADC to continue functioning. The Power-down mode saves the register contents but freezes the Oscillators, disabling all other chip functions until the next interrupt or Hardware Reset. The wake-up or interrupt on pin change features enable the ATtiny15L to be highly responsive to external events, still featuring the lowest power consumption while in the Power-saving modes.

 The device is manufactured using Atmel’s high-density, Non-volatile memory technology.
By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny15L is a
powerful microcontroller that provides a highly flexible and cost-efficient solution to
many embedded control applications. The peripheral features make the ATtiny15L particularly
suited for battery chargers, lighting ballasts and all kinds of intelligent sensor
The ATtiny15L AVR is supported with a full suite of program and system development tools including macro assemblers, program debugger/simulators, In-circuit emulators and evaluation kits.

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General Description
Note: This product is currently in development. - ALL specifications are design targets and are subject to change.

 The ADC083000 is a single, low power, high performance CMOS analog-to-digital converter that digitizes signals to 8 bits resolution at sampling rates up to 3.4 GSPS. Consuming a typical 1.8 Watts at 3 GSPS from a single 1.9 Volt supply, this device is guaranteed to have no missing codes over the full operating temperature range.

 The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters up to Nyquist, producing a high 7.0 Effective Number Of Bits, (ENOB) with a 748 MHz input signal and a 3 GHz sample rate while providing a 10-18 Bit Error Rate, (BER).
 The ADC083000 achieves a 3 GSPS sampling rate by utilizing both the rising and falling edge of a 1.5 GHz input clock. Output formatting is offset binary and the LVDS digital outputs are compliant with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage
between 0.8V and 1.2V.
The ADC has a 1:4 demultiplexer that feeds four LVDS buses and reduces the output data rate on each bus to a quarter of the sampling rate. The ADC can be programmed into the 1:2 Output Mode where the data is output on the Dc and Dd channels at the rate of the input clock.

 The converter typically consumes less than 20 mW in the Power Down Mode and is available in a 128-lead, thermally enhanced exposed pad LQFP and operates over the Industrial
(-40°C ≤ TA ≤ +85°C) temperature range.

■ Internal Sample-and-Hold
■ Single +1.9V ±0.1V Operation
■ Choice of SDR or DDR output clocking
■ 1:2 or 1:4 Selectable Output Demux
■ Clock Phase Adjust for Multiple ADC Synchronization
■ Guaranteed No Missing Codes
■ Serial Interface for Extended Control
■ Adjustment of Input Full-Scale Range and Offset
■ Duty Cycle Corrected Sample Clock
■ Test pattern

 Key Specifications
■ Resolution 8 Bits
■ Max Conversion Rate 3 GSPS (min)
■ Bit Error Rate (BER) 10-18 (typ)
■ ENOB @ 748 MHz Input 7.0 Bits (typ)
■ SNR @ 748 MHz 44 dB (typ)
■ Full Power Bandwidth 3 GHz (typ)
■ Power Consumption
— Operating 1.8 W (typ)
— Power Down Mode 20 mW (typ)

■ Direct RF Down Conversion
■ Digital Oscilloscopes
■ Satellite Set-top boxes
■ Communications Systems
■ Test Instrumentation

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1.1 Description
The GMS81C4040/GMS87C4060 is an advanced CMOS 8-bit microcontroller with 40K(60K) bytes of ROM. The device is one of GMS800 family. The HYUNDAI’s GMS81C4040/GMS87C4060 is a powerful microcontroller which provides a highly flexible and cost effective solution to many TV applications. The GMS81C4040/GMS87C4060 provides the following standard features: 40K(60K) bytes of ROM, 1,536 bytes of RAM, 8-bit timer/counter .

1.2 Features
• 40K(60K) Bytes On-chip Program Memory
• 1,536 Bytes of On-chip Data RAM (Included 256 bytes stack memory)
• Instruction Cycle Time (ex:NOP)
- 0.5us at 8MHz
• 40 Programmable I/O pins
- 33 I/O and 7 Output pins
• Serial I/O : 8bit x 1ch
• I2C Bus interface
- Multimaster (2 Pairs interface pins)
• A/D Converter : 8bit x 6ch (TBD LSB)
• Pulse Width Modulation
- 14bit x 1ch
- 8bit x 6ch
• Timer
- Timer/Counter : 8bit x 4ch (16bit x 2ch)
- Basic interval timer : 8bit x 1ch
- Watch Dog Timer
• Number of Interrupt sources : 18
• On Screen Display
- Number of characters : 512 (6 characters are reserved for IC test)
- Character size : 12 dots(X) x 16 dots(Y)
- Character display size : Large, Medium, Small
- DIsplay capability : 24Characters x 16 Line (Two line VRAM buffer)
- Character, Back ground color : 16kinds
- Special functions : Rounding, Outline, Sprite, Shadow,...
• Buzzer Driving port
- 500Hz ~ 250kHz @8MHz (Duty 50%)
• Operating Range : 4.5V to 5.5V


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· 500-MSPS Sample Rate
· 12-Bit Resolution, 10.5 Bits ENOB
· 2-GHz Input Bandwidth
· SFDR = 75 dBc at 450 MHz and 500 MSPS
· SNR = 64.6 dBFS at 450 MHz and 500 MSPS
· 2.2-Vpp Differential Input Voltage
· LVDS-Compatible Outputs
· Total Power Dissipation: 2.2 W
· Offset Binary Output Format
· Output Data Transitions on the Rising and Falling Edges of a Half-Rate Output Clock

· On-Chip Analog Buffer, Track and Hold, and Reference Circuit
· 80-Pin TQFP PowerPAD™ Package (14-mm ´ 14-mm)
· Industrial Temperature Range = –40°C to 85°C
· Pin-Similar to ADS5440/ADS5444
· Test and Measurement Instrumentation
· Software-Defined Radio
· Data Acquisition
· Power Amplifier Linearization
· Communication Instrumentation
· Radar

 The ADS5463 is a 12-bit, 500-MSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. The ADS5463 input buffer isolates the internal switching of the onboard track and hold (T&H) from disturbing the signal source while providing a high-impedance input. An internal reference generator is also provided to simplify the system design.

 Designed to optimize conversion of wide-bandwidth signals up to 500 MHz of input frequency at 500 MSPS, the ADS5463 has outstanding low noise and linearity over a large input frequency range. Input signals above 500 MHz can also be converted due to the large input bandwidth of the device.

 The ADS5463 is available in an 80-pin TQFP PowerPAD™ package. The ADS5463 is built on state-of-the-art Texas Instruments complementary bipolar process (BiCom3X) and is specified over the full industrial temperature range (–40°C to 85°C).


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