General Description
 The S25FL016A is a 3.0 Volt (2.7 V to 3.6 V), single-power-supply Flash memory device.
The device consists of thirty-two sectors, each with 512 Kb memory.
The device accepts data written to SI (Serial Input) and outputs data on SO (Serial Output).
The devices are designed to be programmed in-system with the standard system 3.0 volt VCC supply.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program command. The device supports Sector Erase and Bulk Erase commands.
Each device requires only a 3.0 volt power supply (2.7 V to 3.6 V) for both read and write functions.
Internally generated and regulated voltages are provided for the program operations.
This device does not require a VPP supply.

Distinctive Characteristics
* Single power supply operation
– Full voltage range: 2.7 to 3.6 V read and program operations
* Memory Architecture
– Thirty-two sectors with 512 Kb each
* Program
– Page Program (up to 256 bytes) in 1.4 ms (typical)
– Program operations are on a page by page basis
* Erase
– 0.5 s typical sector erase time
– 10 s typical bulk erase time
* Cycling Endurance
– 100,000 cycles per sector typical
* Data Retention
– 20 years typical
* Device ID
– JEDEC standard two-byte electronic signature
– RES command one-byte electronic signature for backward compatibility
* Process Technology
– Manufactured on 0.20 μm MirrorBit® process technology
* Package Option
– Industry Standard Pinouts
– 16-pin SO package (300 mils)
– 8-pin SO package (208 mils)
– 8-Contact WSON Package (6x8 mm), Pb Free Performance Characteristics
* Speed
– 50 MHz clock rate (maximum)
* Power Saving Standby Mode
– Standby Mode 50 μA (max)
– Deep Power Down Mode 1.3 μA (typical) Memory Protection Features
* Memory Protection
– W# pin works in conjunction with Status Register Bits to protect specified memory areas
– Status Register Block Protection bits (BP2, BP1, BP0) in status register configure parts of memory as read-only

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The CS1009 is a precision trimmed 2.5 V ±5.0 mV shunt regulator diode. The low dynamic impedance and wide operating current range enhances its versatility. The tight reference tolerance is achieved by on–chip trimming which minimizes voltage tolerance and temperature drift.
A third terminal allows the reference voltage to be adjusted ±5.0% to calibrate out system errors. In many applications, the CS1009GZ can be used as a pin–to–pin replacement of the LT1009CZ and the LM136Z–2.5 with the external trim network eliminated.

Features
• 0.2% Initial Tolerance Max.
• Guaranteed Temperature Stability
• Maximum 0.6 W Dynamic Impedance
• Wide Operating Current Range
• Directly Interchangeable with LT1009 and LM136 for Improved Performance
• No Adjustments Needed for Minimum Temperature Coefficient
• Meets Mil Std 883C ESD Requirements

CS1009GD8
CS1009GDR8
CS1009GZ3
CS1009GZR3

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DISTINCTIVE CHARACTERISTICS

ARCHITECTURAL ADVANTAGES
■ Single power supply operation
— 3 volt read, erase, and program operations
■ VersatileI/OTM control
— Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V
■ Manufactured on 0.23 µm MirrorBitTM process technology
■ SecSi™ (Secured Silicon) Sector region
— 128-doubleword/256-word sector for permanent, secure identification through an 8 doubleword/16-word random Electronic Serial Number, accessible through a command sequence
— May be programmed and locked at the factory or by the customer
■ Flexible sector architecture
— One hundred twenty-eight 32 Kdoubleword (64 Kword) sectors
■ Compatibility with JEDEC standards
— Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection
■ 100,000 erase cycles per sector
■ 20-year data retention at 125°C
PERFORMANCE CHARACTERISTICS
■ High performance
— 100 ns access time
— 30 ns page read times
— 0.5 s typical sector erase time
— 22 µs typical write buffer doubleword programming time: 16-doubleword/32-word write buffer reduces overall programming time for multiple-word updates
— 4-doubleword/8-word page read buffer
— 16-doubleword/32-word write buffer
■ Low power consumption (typical values at 3.0 V, 5 MHz)
— 26 mA typical active read current
— 100 mA typical erase/program current
— 2 µA typical standby mode current
■ Package options
— 80-ball Fortified BGA
SOFTWARE & HARDWARE FEATURES
■ Software features
— Program Suspend & Resume: read other sectors before programming operation is completed
— Erase Suspend & Resume: read/program other sectors before an erase operation is completed
— Data# polling & toggle bits provide status
— Unlock Bypass Program command reduces overall multiple-word or byte programming time
— CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices
■ Hardware features
— Sector Group Protection: hardware-level method of preventing write operations within a sector group
— Temporary Sector Unprotect: VID-level method of changing code in locked sectors
— WP#/ACC input accelerates programming time
(when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings
— Hardware reset input (RESET#) resets device
— Ready/Busy# output (RY/BY#) detects program or erase cycle completion


GENERAL DESCRIPTION
 The Am29LV6402M consists of two 64 Mbit, 3.0 volt single power supply flash memory devices and is organized as 4,194,304 doublewords or 8,388,608 words. The device has a 32-bit wide data bus that can also function as an 16-bit wide data bus by using the WORD# input. The device can be programmed either in the host system or in standard EPROM programmers.

 An access time of 100 or 110 ns is available. Note that each access time has a specific operating voltage range (VCC) as specified in the Product Selector Guide and the Ordering Information sections. The device offered in an 80-ball Fortified BGA package. Each device
has separate chip enable (CE#), write enable WE#) and output enable (OE#) controls.
Each device requires only a single 3.0 volt power supply for both read and write functions. In addition VCC input, a high-voltage accelerated program WP#/ACC) input provides shorter programming times through increased current. This feature is intended facilitate factory throughput during system production, but may also be used in the field if desired.

 The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the device using standard microprocessor write timing. Write cycles also internally latch addresses and data needed for the programming and erase operations.

 The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase operation has begun, the host system need only poll the DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 oggle) status bits or monitor the Ready/Busy# RY/BY#) outputs to determine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces command sequence overhead requiring only two write cycles to program data instead of four.

 The VersatileI/O™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os the same voltage level that is asserted on the VIO pin. Refer to the Ordering Information section for valid VIO options.
Hardware data protection measures include a low

 VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming
equipment.

 The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Suspend/ Program Resume feature enables the host system
to pause a program operation in a given sector to read any other sector and then complete the program operation.

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FEATURES
• Access time: 70ns
• Simple byte and page write
—Single 5V supply
—No external high voltages or VPP control circuits
—Self-timed
—No erase before write
—No complex programming algorithms
—No overerase problem
• Low power CMOS
—Active: 60mA
—Standby: 500µA
• Software data protection
—Protects data against system level inadvertent writes
• High speed page write capability
• Highly reliable Direct Write™ cell
—Endurance: 1,000,000 cycles
—Data retention: 100 years
• Early end of write detection
—DATA polling
—Toggle bit polling
• Pb-free plus anneal available (RoHS compliant)

DESCRIPTION
 The X28HC256 is a second generation high performance CMOS 32K x 8 EEPROM. It is fabricated with Intersil’s proprietary, textured poly floating gate technology, providing a highly reliable 5 Volt only nonvolatile memory.

 The X28HC256 supports a 128-byte page write operation, effectively providing a 24µs/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. The X28HC256 also features DATA Polling and Toggle Bit Polling, two methods of providing early end of write detection. The X28HC256 also supports the JEDEC standard Software Data Protection feature for protecting against inadvertent writes during power-up and power-down.
Endurance for the X28HC256 is specified as a minimum 1,000,000 write cycles per byte and an inherent data retention of 100 years.

X28HC256S-12 X28HC256SZ-12 X28HC256SI-12 X28HC256SIZ-12 X28HC256SM-12
X28HC256D-90 X28HC256DI-90 X28HC256DM-90 X28HC256DMB X28HC256EM-90
X28HC256EMB X28HC256FI-90 X28HC256FM-90 X28HC256FMB-90 X28HC256J-90
X28HC256JZ-90 X28HC256JI-90 X28HC256JIZ-90 X28HC256JM-90 X28HC256KM-90
X28HC256KMB X28HC256P-90 X28HC256PZ-90 X28HC256PI-90 X28HC256PIZ-90
X28HC256S-90 X28HC256SI-90 X28HC256SIZ-90
TAG byte, EEPROM, Volt

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DISTINCTIVE CHARACTERISTICS
* Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications
— Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with
high performance 3.3 volt microprocessors
* Manufactured on 0.35 mm process technology
— Compatible with 0.5 mm Am29LV400 device
* High performance
— Full voltage range: access times as fast as 80 ns
— Regulated voltage range: access times as fast as 70 ns
* Ultra low power consumption (typical values at 5 MHz)
— 200 nA Automatic Sleep mode current
— 200 nA standby mode current
— 7 mA read current
— 15 mA program/erase current
* Flexible sector architecture
— One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and seven 64 Kbyte sectors (byte mode)
— One 8 Kword, two 4 Kword, one 16 Kword, and seven 32 Kword sectors (word mode)
— Supports full chip erase
— Sector Protection features:
A hardware method of locking a sector to prevent any program or erase operations within
that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors
* Unlock Bypass Program Command
— Reduces overall programming time when issuing multiple program command sequences
* Top or bottom boot block configurations available
* Embedded Algorithms
— Embedded Erase algorithm automatically preprograms and erases the entire chip or any
combination of designated sectors
— Embedded Program algorithm automatically writes and verifies data at specified addresses
* Minimum 1,000,000 write cycle guarantee per sector
* Package option
— 48-ball FBGA
— 48-pin TSOP
— 44-pin SO
* Compatibility with JEDEC standards
— Pinout and software compatible with singlepower supply Flash
— Superior inadvertent write protection
* Data# Polling and toggle bits
— Provides a software method of detecting program or erase operation completion
* Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or erase cycle completion
* Erase Suspend/Erase Resume
— Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation
* Hardware reset pin (RESET#)
— Hardware method to reset the device to reading array data

GENERAL DESCRIPTION
 The Am29LV400B is a 4 Mbit, 3.0 volt-only Flash memory organized as 524,288 bytes or 262,144 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system using only a single 3.0 volt VCC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers.

 This device is manufactured using AMD’s 0.35 mm process technology, and offers all the features and benefits of the Am29LV400, which was manufactured using 0.5 mm process technology. In addition, the Am29LV400B features unlock bypass programming and in-system sector protection/unprotection.
The standard device offers access times of 70, 80, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls.

 The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.

 Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facilitates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence.
 This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin.

 The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command.
The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory.
This can be achieved in-system or via programming equipment.

 The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the
system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes.

 AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling.
The data is programmed using hot electron injection.

AM29LV400B Am29LV400BT70REC Am29LV400BB70REC Am29LV400BT80EC   
Am29LV400BB80EC Am29LV400BT90EC Am29LV400BB90EC Am29LV400BT120EC   
Am29LV400BB120EC Am29LV400BT70RFC Am29LV400BB70RFC Am29LV400BT80FC   
Am29LV400BB80FC Am29LV400BT90FC Am29LV400BB90FC

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