General description
The 74AUP1G74 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G74 provides the single positive-edge triggered D-type flip-flop with individual data (D) input, clock (CP) input, set (SD) and reset (RD) inputs and complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D input must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Features
*Wide supply voltage range from 0.8 V to 3.6 V
*High noise immunity
*Complies with JEDEC standards:
-JESD8-12 (0.8 V to 1.3 V)
-JESD8-11 (0.9 V to 1.65 V)
-JESD8-7 (1.2 V to 1.95 V)
-JESD8-5 (1.8 V to 2.7 V)
-JESD8-B (2.7 V to 3.6 V)
*ESD protection:
-HBM JESD22-A114-D Class 3A exceeds 5000 V
-MM JESD22-A115-A exceeds 200 V
-CDM JESD22-C101-C exceeds 1000 V
*Low static power consumption; ICC = 0.9 mA (maximum)
*Latch-up performance exceeds 100 mA per JESD 78 Class II
*Inputs accept voltages up to 3.6 V
*Low noise overshoot and undershoot < 10 % of VCC
*IOFF circuitry provides partial Power-down mode operation
*Multiple package options
*Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G74DC, 74AUP1G74GT, 74AUP1G74GM

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AT404 - EZYTRIGGER

ETC 2008/04/16 09:48
 The AT404 EasyTrigger in combination with a fibre optic cable replaces pulse transformers including all associated circuitry in phase controlled thyristor equipment.
It is intended for applications where high insulation voltages or long transmitting distances are important.
Because of the small control current, the unit serves as an ideal link between the control intelligence and the thyristor.
Each unit triggers a single thyristor and is intended for 115 - 690Vrms supplies.
The operation of the AT404 is based on a controlled current source connected between anode and gate of the thyristor to be triggered.
The large gate current is initiated by the output current from a fibre optic receiver diode.
With a suitable transmitter, small and large thyristors can be triggered directly from standard logic circuits without the need of a gate drive power supply.
The receiver diode is not part of the unit.
Among the many possible applications, it is specifically useful in electrostatic precipitators.

APPLICATION INFORMATION
The sensitivity of the fibre optic system is important if it is desirable to drive the AT404 directly from the control logic.
For a receiver diode output above 30mA the turn-on delay is approximately inversely proportional to the current and therefore pulse shaping can reduce the turn-on delay down to a
minimum of about 5mS.
The printed circuit board tracks from the fibre optic receiver to the AT404 EasyTrigger need to be a short as possible.
Furthermore the (+) track should preferably surround the (-) track to minimize capacitive interference from fast rising voltages in the vicinity.
Since the gate current is derived from the anode of the thyristor no gate drive power supply is
required.
It is advisable to maintain the control signal during the entire conduction period of the thyristor. Once the thyristor is triggered, the gate current ceases to flow because the anode voltage
drops below the threshold voltage, which arises because the anode voltage is used as a source for the gate current.
The effect of this threshold voltage is very small because it only limits the minimum regulated output voltage of the controller.
For example with a 115V single phase controller, this minimum voltage is less than 0.3% and on a 400V system it can be safely ignored.
The thyristor is triggered from a current source with a maximum voltage of 22V.
This allows for twisted gate leads of up to 1m without seriously affecting the rate of rise of gate current (di/dt)g.
Note that the envelope of the voltage across the thyristor can have any desired shape provided the rms value is below Vm and the peak value does not exceed Vp.
The connection diagram below shows the typical application of the AT404 EasyTrigger in mains
operated systems using thyristors with current ratings of a few Amps up to several thousand Amps.
TAG ezy, Trigger

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General description
The 74HC2G14; 74HCT2G14 is a high-speed Si-gate CMOS device.
The 74HC2G14; 74HCT2G14 provides two inverting buffers with Schmitt trigger action which accept standard input signals. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.
The inputs switch at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT- is defined as the input hysteresis voltage VH.

Features
* Wide supply voltage range from 2.0 V to 6.0 V
* Complies with JEDEC standard no. 7A
* High noise immunity
* ESD protection:
* HBM JESD22-A114-D exceeds 2000 V
* MM JESD22-A115-A exceeds 200 V
* Low power dissipation
* Balanced propagation delays
* Unlimited input rise and fall times
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

Applications
* Wave and pulse shaper for highly noisy environments
* Astable multivibrators
* Monostable multivibrators

74HC2G14GW
74HC2G14GV
74HCT2G14GW
74HCT2G14GV
TAG dual, Trigger

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FEATURES
* Output capability: standard
* ICC category: flip-flops

GENERAL DESCRIPTION
The 74HC/HCT107 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
 The 74HC/HCT107 are dual negative-edge triggered JK-type flip-flops featuring individual J, K, clock (nCP) and reset (nR) inputs; also complementary Q and Q outputs.
 The J and K inputs must be stable one set-up time prior to the HIGH-to-LOW clock transition for predictable operation.
 The reset (nR) is an asynchronous active LOW input. When LOW, it overrides the clock and data inputs, forcing the Q output LOW and the Q output HIGH. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.

74HCT107

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FEATURES
* Applications:
– Wave and pulse shapers
– Astable multivibrators
– Monostable multivibrators.
* Complies with JEDEC standard no. 7A
* ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
* Specified from -40 to +85 °C and -40 to +125 °C.

DESCRIPTION
 The 74HC14 and 74HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
 The 74HC14 and 74HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals.

74HCT14 74HC14D 74HCT14D 74HC14DB 74HCT14DB 74HC14N 74HCT14N 74HC14PW
74HCT14PW 74HC14BQ 74HCT14BQ

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GENERAL DESCRIPTION
The 74HC/HCT574 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and non-inverting 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition. When OE is LOW, the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high impedance OFF-state.Operation of the OE input does not affect the state of the flip-flops.
The “574” is functionally identical to the “564”, but has non-inverting outputs.
The “574” is functionally identical to the “374”, but has a different pinning.

FEATURES
· 3-state non-inverting outputs for bus oriented applications
· 8-bit positive edge-triggered register
· Common 3-state output enable input
· Independent register and 3-state buffer operation
· Output capability: bus driver
· ICC category: MSI

74HC574D, 74HC574N, 74HC574DB, 74HCT574D, 74HCT574N, 74HCT574DB

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FEATURES
· Output capability : standard
· ICC category : SSI

GENERAL DESCRIPTION
The 74HC/HCT14 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).
They are specified in compliance with JEDEC standard no. 7A.
The 74HC/HCT14 provide six inverting buffers with Schmitt-trigger action. They are capable of transforming slowly
changing input signals into sharply defined, jitter-free output signals.
TAG Trigger

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