Product Highlights
* Non-Transparent PCI-to-PCI bridge technology for high-performance embedded and intelligent I/O applications
* Independent address spaces and asynchronous clocks deliver unparalleled application
flexibility
* 64-bit primary and secondary bus interfaces deliver high performance for data-intensive applications
* Compliant with ACPI and PCI bus power management specifications
* Secondary bus arbitration support for up to nine bus master devices
* Evaluation Design Kit speeds time-to-market
* Fully compliant with Revision 2.3 of the PCI specification including delayed transactions
* Available in 33 and 66 MHz

Product Overview
Intel’s 21555 Non-Transparent PCI-to-PCI bridge chip enables add-in card vendors to deliver high-performance, intelligent option cards and embedded products that previously were not possible. Designed specifically for applications where a processor is used behind a PCI-to-PCI bridge, the 21555 provides a clean architecture for creating a product with multiple processor domains.

Efficient Management of System and Subsystem Resources
The 21555 provides independent primary and secondary address spaces, which allow independent host and local address mapping.
With this key feature, local memory requirements need not impact the host address map. The 21555 performs address translation between the primary and secondary buses, resolving address resource conflicts between the host and local address domains.

 Featuring a subsystem PCI configuration boundary, the 21555 allows the local processor to
have complete PCI configuration control of subsystem devices, without host interference. This
advanced feature also allows the 21555 to present subsystem, such as a RAID controller, as a
single virtual PCI device. An added benefit of this design is the ability to easily identify a single
device driver for the entire subsystem. Another feature of the 21555, a serial ROM interface,
allows manufacturers to customize the 21555 for particular application by pre-loading the ROM
with vendor-specific configuration data.

A Unique Bridge Architecture
Intel’s 21555 is a unique new Non-Transparent PCI-to-PCI bridge solution. The 21555 provides
designers of intelligent controllers and embedded systems with a Non-Transparent PCI to- PCI bridge solution capable of resolving resource conflicts between a PCI-based host system and a PCI-based subsystem. This gives a local processor maximum flexibility in mapping and managing subsystem resources.

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FEATURES:
• 3.3V low voltage advanced BiCMOS technology (LVT) 16- bit transparent D-type latches with 3-state outputs
• Total dose hardness:
- > 100 krad (Si), dependent upon space mission
• Single event effect:
- SELTH : No LU > 119 MeV/mg/cm2
• Package: 48 pin RAD-PAK® flat package
• Operating temperature range: - 55 to 125°C
• Distributed VCC and GND pin configuration minimizes highspeed switching noise
• Supports mixed-mode signal operation
- 5V input and output voltages with 3.3V VCC
• Supports unregulated battery operation down to 2.7V
• Typical VOLP (output ground bounce) < 0.8V at VCC=3.3V, TA=25°C
• Latch-up performance exceeds 500mA per JEDEC standard
• Supports live insertion
• Bus-hold data inputs eliminate the need for external pullup resistors

DESCRIPTION:
Maxwell Technologies’ 54LVTH16373 16-bit transparent Dtype latches with 3-state output features a greater than 100 krad (Si) total dose tolerance, dependent upon space mission.
The 54LVTH16373 is designed for low voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. It is suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
 
 The 54LVTH16373 can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is low, the Q output are latched at the levels set up at the data (D) inputs. When LE is high, the Q outputs follow the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state or a high impedance state. In the high impedance state, the outputs neither load nor drive the bus lines significantly. The high impedance state and the increased drive provide the capability to drive bus lines without the need for interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high impedance state.

 Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S.

54LVTH16373RPFX 54LVTH16373RPFS 54LVTH16373RPFB 54LVTH16373RPFE 54LVTH16373RPFI

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The SN54/ 74LS373 consists of eight latches with 3-state outputs for bus organized system applications. The flip-flops appear transparent to the data (data changes asynchronously) when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup times is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH the bus output is in the high impedance state. The SN54/ 74LS374 is a high-speed, low-power Octal D-type Flip-Flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A buffered Clock (CP) and Output Enable (OE) is common to all flip-flops. The SN54 /74LS374 is manufactured using advanced Low Power Schottky technology and is compatible with all Motorola TTL families.

• Eight Latches in a Single Package
• 3-State Outputs for Bus Interfacing
• Hysteresis on Latch Enable
• Edge-Triggered D-Type Inputs
• Buffered Positive Edge-Triggered Clock
• Hysteresis on Clock Input to Improve Noise Margin
• Input Clamp Diodes Limit High Speed Termination Effects

SN74LS373 SN54LS374 SN74LS374

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General Description
These 8-bit registers feature totem-pole TRI-STATE outputs designed specifically for driving highly-capacitive or relatively low-impedance loads. The high-impedance state and increased
high-logic level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. (Continued)

Features
ㅁ Choice of 8 latches or 8 D-type flip-flops in a single package
ㅁ TRI-STATE bus-driving outputs
ㅁ Full parallel-access for loading
ㅁ Buffered control inputs
ㅁ P-N-P inputs reduce D-C loading on data lines

DM74LS373 DM54LS374 DM74LS374

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