Description
The LXT362 is a fully integrated, combination transceiver for T1 ISDN Primary Rate Interface and general T1 long and short haul applications. It operates over 22 AWG twisted-pair cables from 0 to 6 kft and offers Line Build Outs and pulse equalization settings for all T1 Line Interface Unit (LIU) applications.
LXT362 provides both a serial port for microprocessor control (Host mode) as well as standalone operation (Hardware mode). The device incorporates advanced crystal-less digital jitter attenuation in either the transmit or receive data path starting at 3 Hz. B8ZS encoding/decoding and unipolar or bipolar data I/O are selectable. Loss of signal monitoring and a variety of diagnostic loopback modes can also be selected.

Product Features
*Fully integrated transceiver for Long or Short-Haul T1 interfaces
-Crystal-less digital jitter attenuation
-Select either transmit or receive path
*No crystal or high speed external clock required
*Meets or exceeds specifications in ANSI T1.102, T1.403 and T1.408; and AT&T Pub 62411
*Supports 100 Ω (T1 twisted-pair) applications
*Selectable receiver sensitivity – fully restores the received signal after transmission through a cable with attenuation of either 0 to 26 dB, or 0 to 36 dB @ 772 kHz
*Five Pulse Equalization Settings for T1 short-haul applications
*Four Line Build-Outs for T1 long-haul applications from 0 dB to -22.5 dB
*Transmit/receive performance monitors with Driver Fail Monitor Open and Loss of Signal outputs
*Selectable unipolar or bipolar data I/O and B8ZS encoding/decoding
*Line attenuation indication output in 2.9 dB steps
*QRSS generator/detector for testing or monitoring
*Local, remote, and analog loopback, plus in-band network loopback code generation and detection
*Multiple register serial interface for microprocessor control
*Available in 28-pin PLCC, 44-pin PQFP, and 44-pin LQFP packages

Applications
*ISDN Primary Rate Interface (ISDN PRI)
*CSU/NTU interface to T1 Service
*Wireless Base Station interface
*T1 LAN/WAN bridge/routers
*T1 Mux; Channel Banks
*Digital Loop Carrier - Subscriber Carrier Systems

249033-001

GENERAL DESCRIPTION
The Aeroflex Laboratories transceiver model ACT4444 is a monolithic transceiver which provides full compliance with Macair and MIL-STD-1553 data bus requirements. The model ACT4444 performs the front-end analog function of inputting and outputting data through a transformer to a MIL-STD-1553 or Macair data bus with a few external components.
The ACT4444 can be considered a "Universal" Transceiver in that it is compatible with MIL-STD-1553A, B, Macair A-3818, A-4905, A-5232 and A-5690.
Design of these transceivers reflects particular attention to active filter performance. This results in low bit and word error rate with superior waveform purity and minimal zero crossover distortion. The ACT4444 active filter design has additional high frequency roll-off to provide the required Macair low harmonic distortion waveform without increasing the pulse delay characteristics significantly.
Efficient transmitter electrical and thermal design provides low internal power dissipation and heat rise at high and well as low duty cycles.
An optional receiver input threshold adjustment can be accomplished by the use of the "External Threshold" terminals.

FEATURES
*Transceiver meets MIL-STD-1553A & B, Macair A3818, A4905, A5232 and A5690 specs
*Bipolar Supply ±15V to ±12V, Logic Supply +5V
*Replacement for function of CT3232 & ACT4404 in new designs
*Voltage source output
*Monolithic construction
*Aeroflex is a Class H & K MIL-PRF-38534 Manufacturer
*Miniature Chipscale Package Bumped Chip Carrier™ (BCC++)

GENERAL DESCRIPTION
The ML5805 is a single chip fully integrated Frequency Shift Keyed (FSK) transceiver developed for a variety of applications operating in the 5.725GHz to 5.850GHz unlicensed ISM band. The ML5805 is mode selectable for operation with digital cordless phones (DSSS or DECT) and higher data rate streaming applications like wireless audio and video.
The ML5805 contains a dual-conversion low-IF receiver with all channel selectivity on chip. IF filtering, IF gain, and demodulation are performed on-chip, eliminating the need for any external IF filters or production tuning. A post detection filter and a data slicer are integrated to complete the receiver.
The ML5805 transmitter uses an adjustment-free closed loop modulator, which modulates the on-chip VCO with filtered data. The ML5805 includes an upconversion mixer, a buffer/predriver, and a power amplifier to produce a typical output power of +21dBm. A fully integrated fractional synthesizer is used in both receive and transmit modes. Power supply regulation is included in the ML5805, providing circuit isolation and consistent performance over supply voltages between 2.8V-3.6V.

FEATURES
*Highly integrated 5.8GHz FSK Transceiver with selectable data rates; 576kbps, 1.152Mbps, 1.536Mbps, 1.755Mpbs, 2.048Mbps
*Fractional-N synthesizer with 30 Hz resolution
*Low-IF receiver eliminates external IF filters
*Fully integrated digital FIR Tx data filter, IF filters, FM discriminator, and Rx data filter.
*Self-calibrating VCO and filters eliminate tuning.
*Operating Modes include DSSS-DCT, DECT, and high rate (2.048Mbps) for wireless audio and video
*-97dBm sensitivity (0.1%BER) with Integrated LNA
*+21dBm typical output power from Integrated PA
*Includes FastWave™ embedded wireless microcontroller technology
*Simple 3-wire control interface
*TR PIN diode or FET switch driver outputs
*Analog RSSI output: 35mV/dB
*Selectable Rx clock recovery output
*40 QFN package (6mm x 6mm)

APPLICATIONS
*Digital Cordless Telephones DSSS & DECT
*Wireless Streaming Audio and Video
*Wireless Data Links

ML5805DM, ML5805DM-T

Description
The LXT9763 is a six-port PHY Fast Ethernet Transceiver that supports IEEE 802.3 physical layer applications at both 10 and 100 Mbps. The mixed-signal adaptive equalization and clock recovery with proprietary Optimal Signal Processing (OSP™) architecture improves SNR 3 dB over ideal analog filters. All six network ports provide a combination twisted-pair (TP) or pseudo-ECL (PECL) interface for a 10/100BASE-TX or 100BASE-FX connection. The LXT9763 supports both half- and full-duplex operation at 10 and 100 Mbps.
A fully independent Media Independent Interface (MII) for each port provides maximum control for switch and multi-port adapter applications.
In addition to an expanded set of MDIO registers, the LXT9763 provides three discrete LED driver outputs for each port. The LXT9763 requires only a single 3.3V power supply.

Product Features
*Six independent IEEE 802.3-compliant 10BASE-T or 100BASE-TX ports with integrated filters.
*Proprietary Optimal Signal Processing™ (OSP™) architecture improves SNR by 3dB over ideal analog filters.
*Baseline wander correction for improved 100BASE-TX performance.
*100BASE-FX fiber-optic capability on all ports.
*Supports both auto-negotiation and legacy systems without auto-negotiation capability.
*JTAG boundary scan.
*Six MII ports for independent PHY port operation.
*Configurable via MDIO port or external control pins.
*Maskable interrupts.
*Very low power 3.3V operation (380 mW per channel, typical).
*208-pin PQFP (0-70 oC ambient temperature range).

Applications
*100BASE-T, 10/100-TX, or 100BASE-FX Switches and multi-port NICs.

Description
The Elan EM198810 IC is a low-cost, fully integrated CMOS radio frequency (RF) transceiver block, combined with a 64-byte buffered framer block. The RF transceiver block is a self-contained, fast-hopping GFSK data modem, optimised for use in the widely available 2.4 GHz ISM band. It contains transmit, receive, VCO and PLL functions, including an on-chip channel filter and resonator, thus minimizing the need for external components. The receiver utilizes extensive digital processing for excellent overall performance, even in the presence of interference and transmitter impairments. Transmit power is digitally controlled. The low-IF receiver architecture results in sensitivity to -80dBm or better, with impressive selectivity.
In normal applications, the EM198810 is connected to a low cost microcontroller(ex:EM78P451S).
In normal application The on-chip framer processes and stores the RF data in the background, unloading this critical timing function from the MCU. This lowers MCU speed requirements, expedites product development time, and frees the MCU for implementing additional product features.
The framer register settings determine the over-the-air formatting characteristics. Many configurations are possible, depending on the user’s specific needs. Raw transmit data is easily sent over-the-air as a complete frame of data, with preamble, address, payload, and CRC. Receiving data is just the opposite, using the preamble to train the receiver clock recovery, then the address is checked, then the data is reverse formatted for receive, followed by CRC. All of this is done in hardware to ease the programming and overhead requirements of the baseband MCU.
For longer battery life, power consumption is minimized by automatic enabling of the various transmit, receive, PLL, and PA sections, depending on the instantaneous state of the chip. A sleep mode is also provided for ultra low current consumption.
This product is available in 32-lead 5x5 mm JEDEC standard QFN package, featuring an exposed pad on the bottom for best RF characteristics. Lead-free RoHS compliant packaging is available on request.

FEATURES
The EM198810 is a CMOS integrated circuit that performs all functions from the antenna to the microcontroller for transmission and reception of a 2.4GHz digital data. This transceiver IC integrates most of the functions required for data transmission into a single integrated circuit. Additionally, the programmability implemented reduces significantly external components count, board space requirements and external adjustments.
Key Features
*Combines 2.4 GHz GFSK RF transceiver with 8-bit data framer function
*Eliminates need for external software or hardware FIFO; offloads MCU for other tasks
*Simple microprocessor interface – 4 wires for SPI, plus 3 wires for RST/buffer control
*Each transmit, receive buffer is 64 bytes deep
*Long packets are possible if buffers are read/written before overflow/underflow occurs
*Always 1Mbps over-the-air symbol rate, regardless of MCU speed or architecture
*Preamble can be 1 to 8 bytes
*Supports 1, 2, 3, or 4 word address (up to 64 bits)
*Various Payload data formats to eliminate DC offset, enhance receive clock recovery and BER
*Programmable data whitening
*Supports Forward Error Correction (FEC): none, 1/3, or 2/3
*Supports 16-bit CRC
*Baseband output clock available
*Power management for minimizing current consumption
*5x5mm QFN package with minimum RF parasitic
*Lead-free packaging and dice is available on request

Applications
*Wireless devices that need quick time-to-market
*Simple and fast wireless data networks
*Cordless headsets and Cellular Phones
*Wireless streaming audio
*Wireless voice and VOIP
*Wireless Skype earphone
*Home and factory automation
*Wireless security and access control
*Battery Powered wireless devices

EM198810W, EM198810H

Description
The HSDL-3202 is a new generation of low-cost Infrared (IR) transceiver modules from Agilent Technologies. It features one of the smallest footprints in the industry at 2.5 H x 8.0 W x 3.0 D mm. Although the supply voltage can range from 2.7 V to 3.6 V, the LED drive current is internally compensated to a constant 32 mA to guarantee link distance of IrDA Data 1.3 (low power) physical layer specification.
The HSDL-3202 meets the link distance of 20 cm to other IrDA 1.3 low power devices, and 30 cm to standard one meter IrDA 1.3 devices. It is designed to interface to input/output logic circuits as low as 1.8 V.

Features
*Ultra small surface mount package
*Minimal height: 2.5 mm
*VCC from 2.7 to 3.6 volts
*Interface to input/output logic circuits as low as 1.8 V
*LED supply voltage can range from 2.7 to 6 volts
*Low ICC shutdown current
-10 nA typical
*Complete shutdown
-TxD, RxD, PIN diode
*Three optional external components
*Temperature performance guaranteed, -25°C to 85°C
*32 mA LED drive current
*Integrated EMI shield
*IEC825-1 class 1 eye safe
*Edge detection input
-prevents the LED from long turn on time

Applications
*Mobile telecom
-cellular phones
-pagers
-smart phones
*Data communication
-PDAs
-portable printers
*Digital imaging
-digital cameras
-photo-imaging printers
*Electronic wallet

GENERAL DESCRIPTION
The S3031B transceiver chip is a fully integrated CMI encoding transmitter and CMI decoding receiver. The chip derives high speed timing and data signals for SONET/SDH or PDH-based equipment. The circuit is implemented using AMCC’s proven Phase Locked Loop (PLL) technology. Figures 1a and 1b show typical network applications.
The S3031B has two independent VCOs which are synchronized to the local NRZ transmitted data and the received CMI data respectively. The chip can be used with either a 19.44 MHz or a 38.88 MHz reference clock when operated in the SONET/SDH OC-3 mode. In E4 mode the chip can be operated with a 17.408 MHz or a 34.816 MHz reference in support of existing system clocking schemes. On-chip coded-mark-inversion (CMI) encoding and decoding is provided for 139.264 Mbps and 155.52 Mbps interfaces.
The low jitter PECL interface for the serial data inputs and the PECL nibble clock interface guarantee compliance with the bit-error rate requirements of the Bellcore and ITU-T standards. The S3031B is packaged in a 0.65 mm pitch 100-pin PQFP/TEP.
The S3031B provides the major active components onchip for a coaxial cable interface, including analog transformer driver circuitry and equalization interface circuitry. Discrete controls permit separate selection of CMI or NRZ operation and analog (coaxial copper) or PECL (optical module) media interfaces. Both line loopback and diagnostic local loopback operation are supported.

FEATURES
*Complies with Bellcore and ITU-T specifications
*On-chip high-frequency PLLs for clock generation and clock recovery
*On-chip analog circuitry for transformer driver and equalization
*Supports 139.264 Mbps (E4) and 155.52 Mbps (OC-3) transmission rates
*Supports 139.264 Mbps and 155.52 Mbps Coded Mark Inversion (CMI) interfaces
*TTL Reference frequencies of 19.44 and 38.88 MHz (OC-3) or 17.408 and 34.816 MHz (E4)
*Interface to both PECL and TTL logic
*Lock detect on clock recovery function — monitors run length and frequency
*Serial and 4 bit (nibble) system interfaces
*Low jitter PECL interface
*+5V operation
*100 PQFP/TEP package
*Supports both electrical and optical interfaces

APPLICATIONS
*ATM over SONET/SDH
*OC-3/STM-1 or E4-based transmission systems
*OC-3/STM-1 or E4 modules
*OC-3/STM-1 or E4 test equipment
*Section repeaters
*Add Drop Multiplexers (ADM)
*Broadband cross-connects
*Fiber optic terminators
*Fiber optic test equipment

S3031BH0

GENERAL DESCRIPTION
The ML2726 is a fully integrated 2.0Mbps frequency shift keyed (FSK) transceiver that operates in the unlicensed 2.4GHz ISM frequency band. The device has been optimized for digital cordless telephone applications and includes all the frequency generation, receive and transmit functions. Automatically adjusted filters eliminate mechanical tuning. Closed loop modulation eliminates frequency drift and permits practically unlimited TX duration. The transmitter generates a 3dBm FSK output signal.
The 2.0Mbps data rate permits data spreading, such as Direct Sequence Spread Spectrum (DSSS) modulation, which improves range. The dual conversion Low-IF receiver has all of the sensitivity and selectivity advantages of a traditional super-heterodyne without requiring costly, bulky external filters, while providing the integration advantages of direct conversion.
The phase locked loop (PLL) synthesizer is completely integrated, including the voltage controlled oscillator (VCO), tuning circuits, and VCO resonator. This allows the ML2726 to be used in frequency hopped spread spectrum (FHSS) applications.
The ML2726 contains internal voltage regulation. It also contains PLL and transmitter configuration registers. The device can be placed in a low power standby mode for current sensitive applications. It is packaged in a “Green” Pb-Free 32TQFP.

FEATURES
*Complete 2.4GHz FSK Transceiver
-High data rate (2.048 Mbps)
--80dBm sensitivity @ 0.1% BER (typ)
-3dBm Output Power (differential, typ)
*Closed Loop TX Modulation
*Low IF Receiver: No external IF filters required.
*Fully Integrated frequency synthesizer:
-No external resonator required.
*Sigma-Delta Fractional-N two-port modulator
*Automatic Filter Alignment
-No manufacturing adjustments required.
*No external data slicer components required
*Control outputs correctly sequence and control PA
*3-wire control interface
*Analog RSSI output

APPLICATIONS
*2.4GHz FSK Data Transceivers
-Digital Cordless Telephones
-Wireless PC Peripherals
-Wireless Game Controllers
-Wireless Streaming Media

ML2726DH, ML2726DH-T

Description
The Intel® LXT972M Single-Port 10/100 Mbps PHY Transceiver is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both 100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for easy attachment to 10/100 Media Access Controllers (MACs). Both full and half-duplex operation at 10 Mbps and 100 Mbps is supported.
Operation mode can be set to auto-negotiation, parallel detection, or manual control. The device is powered from a single 3.3V power supply.

Product Features
*3.3V Operation
*IEEE 802.3-compliant 10BASE-T or 100BASE-TX with integrated filters
*Auto-negotiation and parallel detection
*MII interface with extended register capability
*Robust baseline wander correction
*Carrier Sense Multiple Access / Collision Detection (CSMA/CD) or full-duplex operation
*JTAG boundary scan
*MDIO serial port or hardware pin configurable
*Integrated, programmable LED drivers
*48-pin Low-profile Quad Flat Package

Applications
*Combination 10BASE-T/100BASE-TX Network Interface Cards (NICs)
*Wireless access points
*Network printers
*10/100 Personal Computer Memory Card International Association (PCMCIA) cards
*Cable Modems and Set-Top Boxes

DJLXT972MLC.A4, WJLXT972MLC.A4

Description
ATA6612/ATA6613 is a System-in-Package (SiP) product, which is particularly suited for complete LIN-bus slave-node applications. It supports highly integrated solutions for in-vehicle LIN networks. The first chip is the LIN-system-basis-chip (LIN-SBC) ATA6624, which has an integrated LIN transceiver, a 5V regulator and a window watchdog. The second chip is an automotive microcontroller from Atmel®’s series of AVR 8-bit microcontroller with advanced RISC architecture.
The ATA6612 consists of the LIN-SBC ATA6624 and the ATmega88 with 8 Kbytes flash. The ATA6613 consists of the LIN-SBC ATA6624 and the ATmega168 with 16 Kbytes flash. All pins of the LIN System Basis Chip as well as all pins of the AVR microcontroller are bonded out to provide customers the same flexibility for their applications as they have when using discrete parts.
In section 2 you will find the pin configuration for the complete SiP. In sections 3 to 5 the LIN SBC is described, and in sections 6 to 7 the AVR is described in detail.

General Features
*Single-package Fully-integrated AVR® 8-bit Microcontroller with LIN Transceiver, 5V Regulator and Watchdog
*Very Low Current Consumption in Sleep Mode
*8 Kbytes/16 Kbytes Flash Memory for Application Program (ATA6612/ATA6613)
*Supply Voltage Up to 40V
*Operating Voltage: 5V to 27V
*Temperature Range: Tcase –40°C to +125°C
*QFN48, 7 mm × 7 mm Package

ATA6613, ATA6612P-PLQW, ATA6612P-PLPW, ATA6613P-PLQW, ATA6613P-PLPW