DESCRIPTION
The AZ100ELT23 is a dual differential PECL to CMOS/TTL translator. Because PECL (Positive ECL) levels are used, only VCC and ground are required. The small outline 8-lead packaging and the low skew, dual gate design of the ELT23 makes it ideal for applications that require the translation of a clock and a data signal.
The ELT23 is available in only the ECL 100K standard. Since there are no PECL outputs or an external VBB reference, the ELT23 does not require both ECL standard versions. The PECL inputs are differential; there is no specified difference between the differential input 10K and 100K standards. Therefore the AZ100ELT23 can accept any standard differential PECL input referenced from a VCC of 3.0V to 5.5V.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.

FEATURES
*Green / RoHS Compliant / Lead (Pb) Free package available
*3.5ns Typical Propagation Delay
*<500ps Typical Output to Output Skew
*Differential PECL Inputs
*CMOS/TTL Outputs
*Flow Through Pinouts
*Direct Replacement for ON Semiconductor MC100ELT23
*Operating Range of 3.0V to 5.5V (For operation down to 2.5V consult AZM)
*Use AZ100ELT23 for 10K Applications

AZ100ELT23D, AZ100ELT23D+, AZ100ELT23DG, AZ100ELT23T, AZ100ELT23T+
TAG CMOS, TTL

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FUNCTIONAL DESCRIPTION
The DDU39F-series device is a mechanically variable, FAST-TTL interfaced delay line.
The signal input (IN) is reproduced at the tap output (OUT), shifted by an amount which can be adjusted between 7ns and 25ns.
The device operates from a single 5V supply and is TTL interfaced, capable of driving up to 10 TTL loads.

FEATURES
*Ideal for “Set and Forget” applications
*Multi-turn adjustment screw (approx. 15 turns)
*Fits standard 16-pin DIP socket
*Input & output fully TTL interfaced & buffered (10 T2L fan-out capability)
*Resolution: 0.5ns typical
*Adjustment range: 7ns to 25ns
*Output rise time: 4ns typical
*Min. input pulse width: 10ns
*Power dissipation: 230mW maximum
*Operating temperature: 0° to 70°C (Commercial) -55° to 125°C (Military)

APPLICATION NOTES
*HIGH FREQUENCY RESPONSE
The DDU39F tolerances are guaranteed for input pulse widths and periods greater than those
specified in the test conditions.
Although the device will function properly for pulse widths as small as 10ns and periods as small 20ns (for a symmetric input), the delays may deviate from their values at low frequency.
However, for a given input condition, the deviation will be repeatable from pulse to pulse.
Contact technical support at Data Delay Devices if your application requires device testing at a specific input condition.
*POWER SUPPLY BYPASSING
The DDU39F relies on a stable power supply to produce repeatable delays within the stated
tolerances.
A 0.1uf capacitor from VCC to GND, located as close as possible to the VCC pin, is recommended.
A wide VCC trace and a clean ground plane should be used.

DDU39F
DDU39FM
TAG TTL

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DESCRIPTION
 The AZ10/100ELT20 is a CMOS/TTL to differential PECL translator.
It operates with a single power supply of +3.0 to +5.5 volts, making it ideal for both LVCMOS/LVTTL and CMOS/TTL applications.
The extremely small MLP 8 2x2 mm package makes it ideal for those applications where space, performance and low power are at a premium.
When the D input is left floating, the Q output is forced HIGH, and the Q¯ output is forced LOW. The ELT20 is available in both PECL standards: the AZ10ELT20 is compatible with PECL 10K logic levels while the AZ100ELT20 is compatible with PECL 100K logic levels.

FEATURES
* 0.5ns Typical Propagation Delay
* Differential PECL Outputs
* Flow Through Pinouts
* Operating Range of +3.0V to +5.5V
* Direct Replacement for ON Semi MC10ELT20, MC100ELT20, MC100LVELT20 & Micrel SY89329V
* Available in 2x2 and 3x3 mm MLP Packages
* IBIS Model Files Available on Arizona Microtek Website

AZ100ELT20
AZ100ELT20D
AZ100ELT20DG
AZ100ELT20TG
AZ10/100ELT20XP

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