The P10C68 and P11C68 are fast static RAMs (35 and 45 ns) with a non-volatile electically-erasable PROM (EEPROM) cell incorporating in each static memory cell. The SRAM can be read and written an unlimited number of times while independent non-volatile data resides in PROM.
On the P10C68 data may easily be transferred from the SRAM to the EEPROM (STORE) and from the EEPROM back the SRAM ( RECALL) using the NE (bar) pin. The Store and
Recall cycles are initiated through software sequences on the P11C68. These devices combine the high performance and ease of use of a fast SRAM with the data integrity of nonvolatility.
The P10C68 and P11C68 feature the industry standard pinout for non-volatile RAMs in a 28-pin 0.3-inch plastic and ceramic dual-in-line packages.

FEATURES
* Non-Volatile Data Integrity
* 10 year Data Retention in EEPROM
* 35ns and 45ns Address and Chip Enable Access Times
* 20ns and 25ns Output Enable Access
* Unlimited Read and Write to SRAM
* Unlimited Recall Cycles from EEPROM
* 104 Store Cycles to EEPROM
* Automatic Recall on Power up
* Automatic Store Timing
* Hardware Store Protection
* Single 5V * 10% Operation
* Available in Standard Package 28-pin 0.3-inch DIL plastic and ceramic
* Commercial and Industrial temperature ranges


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Features
• 4.5V-5.5V operation
• CMOS for optimum speed/power
• Low active power
-660 mW (max.)
• Low standby power (L version)
-2.75 mW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE options

Functional Description
The CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 99% when deselected.
Writing to the device is accomplished by taking chip enable one (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking chip enable one (CE) and output enable (OE) LOW while forcing write enable (WE). Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148 is available in a standard 450-mil-wide body width SOIC package.

CY62148-55SC
CY62148L-55SC
CY62148-70SC
CY62148L-70SC
CY62148-70SI
CY62148L-70SI

TAG RAM, Static

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FEATURES
• High-speed access times: 8, 10, 12 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for greater noise immunity
• Easy memory expansion with CE and OE options
• CE power-down
• Fully static operation: no clock or refresh required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
– 32-pin STSOP (Type I)
– 36-pin BGA (8mmx10mm)
• Lead-free Available

DESCRIPTION
The ISSI IS63LV1024/IS63LV1024L is a very high-speed, low power, 131,072-word by 8-bit CMOS static RAM in revolutionary pinout. The IS63LV1024/IS63LV1024L is fabricated using ISSI's high-performance CMOS technology.
This highly reliable process coupled with innovative circuit design techniques, yields higher performance and low power consumption devices.
When CE is HIGH (deselected), the device assumes a standby mode at which the power dissipation can be reduced down to 250 μW (typical) with CMOS input levels.
The IS63LV1024/IS63LV1024L operates from a single 3.3V power supply and all inputs are TTL-compatible.

IS63LV1024L
TAG CMOS, Static

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Features
• High speed
—tAA = 12 ns
• CMOS for optimum speed/power
• Low active power
—1320 mW (max.)
• Automatic power-down when deselected
• Independent Control of Upper and Lower bits
• Available in 44-pin TSOP II and 400-mil SOJ

Functional Description
The CY7C1021 is a high-performance CMOS static RAM organized as 65,536 words by 16 bits. This device has an automatic power-down feature that significantly reduces power consumption when deselected. Writing to the device is accomplished by taking Chip Enable
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O1 through I/O8), is written into the location specified on the address pins (A0 through A15). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O9 through I/O16) is written into the location specified on the address pins (A0 through A15).
 
 Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing the write enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on I/O1 to I/O8. If Byte High Enable (BHE) is LOW, then data from memory will appear on I/O9 to I/O16. See the truth table at the back of this data sheet for a complete description of read and write modes.

 The input/output pins (I/O1 through I/O16) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), the BHE and BLE are disabled (BHE, BLE HIGH), or during a write operation (CE LOW, and WE LOW). The CY7C1021 is available in standard 44-pin T Type II and 400-mil-wide SOJ packages

CY7C1021-10VC
CY7C1021-10ZC
CY7C1021L-10ZC
CY7C1021-12VC
CY7C1021-12VI
CY7C1021-12ZC
CY7C1021-15VC
CY7C1021-15VI
CY7C1021-15ZC
CY7C1021-15ZI
CY7C1021L-15ZC
CY7C1021-20VC
CY7C1021-20ZCSOP
TAG RAM, Static

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