DESCRIPTION
The TAS5352A is a high-performance, integrated stereo digital amplifier power stage designed to drive a 4-Ω bridge-tied load (BTL) at up to 125 W per channel with low harmonic distortion, low integrated noise, and low idle current.
The TAS5352A has a complete protection system integrated on-chip, safeguarding the device against a wide range of fault conditions that could damage the system. These protection features are short-circuit protection, over-current protection, under voltage protection, over temperature protection, and a loss of PWM signal (PWM activity detector).
A power-on-reset (POR) circuit is used to eliminate power-supply sequencing that is required for most power-stage designs.

FEATURES
*Total Power Output (Bridge Tied Load)
-2 × 125 W at 10% THD+N Into 4 Ω
-2 × 100 W at 10% THD+N Into 6 Ω
*Total Power Output (Single Ended)
-4 × 45 W at 10% THD+N Into 3 Ω
-4 × 35 W at 10% THD+N Into 4 Ω
*Total Power Output (Parallel Mode)
-1 × 250 W at 10% THD+N Into 2 Ω
-1 × 195 W at 10% THD+N Into 3 Ω
*>110 dB SNR (A-Weighted With TAS5518 Modulator)
*<0.1% THD+N (1 W, 1 kHz)
*Supports PWM Frame Rates of 192 kHz to 432 kHz
*Resistor-Programmable Current Limit
*Integrated Self-Protection Circuitry, Including:
-Under Voltage Protection
-Overtemperature Warning and Error
-Overload Protection
-Short-Circuit Protection
-PWM Activity Detector
*Standalone Protection Recovery
*Power-On Reset (POR) to Eliminate System Power-Supply Sequencing
*High-Efficiency Power Stage (>90%) With 80-mΩ Output MOSFETs
*Thermally Enhanced 44-Pin HTSSOP Package (DDV)
*Error Reporting, 3.3-V and 5.0-V Compliant
*EMI Compliant When Used With Recommended System Design

APPLICATIONS
*Mini/Micro Audio System
*DVD Receiver
*Home Theater

TAS5352ADDV

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The MC14024B is a 7−stage ripple counter with short propagation delays and high maximum clock rates. The Reset input has standard noise immunity, however the Clock input has increased noise immunity due to Hysteresis. The output of each counter stage is buffered.

Features
• Diode Protection on All Inputs
• Output Transitions Occur on the Falling Edge of the Clock Pulse
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low−power TTL Loads or One Low−power Schottky TTL Load Over the Rated Temperature Range
• Pin−for−Pin Replacement for CD4024B
• Pb−Free Packages are Available

MC14024BCP MC14024BCPG MC14024BD MC14024BDG MC14024BDR2 MC14024BDR2G
MC14024BFEL MC14024BFELG

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