The GS9032 encodes and serializes SMPTE 125M and 244M bit parallel digital video signals, and other 8-bit or 10-bit parallel formats. This device performs sync detection, parallel to serial conversion, data scrambling (using the X9 + X4 + 1 algorithm), 10x parallel clock multiplication and conversion of NRZ to NRZI serial data. The GS9032 features auto standard and adjustment free operation for data rates to 540Mb/s with a single VCO resistor. Other features include a lock detect output, NRZI encoding, SMPTE scrambler bypass, a sync detect disable, and an isolated quad output cable driver suitable for driving 75Ω loads. The complementary cable driving output swings
can be adjusted independently or the secondary differential cable driver can be powered down.
The GS9032 requires a single +5 volt or -5 volt supply and typically consumes 675mW of power while driving four 75Ω loads.

*SMPTE 259M and 540Mb/s compliant
*serializes 8-bit or 10-bit data
*autostandard, adjustment free operation
*minimal external components (no loop filter components required)
*isolated, quad output, adjustable cable driver
*power saving secondary cable driver disable
*3.3V and 5.0V CMOS/TTL compatible inputs
*lock detect indication
*SMPTE scramble and NRZI coding bypass option
*EDH support with GS9001, GS9021
*Pb-free and RoHS Comliant

SMPTE 259M and 540Mb/s parallel to serial interfaces for video cameras, VTRs, and signal generators; generic parallel to serial conversion.

GS9032-CVM, GS9032-CTM, GS9032-CVME3, GS9032-CTME3

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The FIN212AC μSerDes™ is a low-power serializer / deserializer optimized for use in cell phone displays and camera paths. The device reduces a 12-bit data path to four wires. The device can be configured as a serializer or deserializer through the DIRI pin, minimizing
component types in the system. For camera applications, an additional master clock can be passed in the opposite direction of data flow.
The device utilizes Fairchild’s proprietary ultra-low power, low-EMI technology. LV-CMOS parallel output buffers have been implemented with slew rate control to adjust for capacitive loading and to minimize EMI. The device also supports an ultra-low power-down mode for
conserving power in battery-operated applications.
The device is available in a 5x5mm MLP package to attach directly to a flex circuit, or in two choices of BGA, where space constraints are a concern.

*Low Power Consumption
*Low Power, Proprietary, CTL™ I/O Serial Interface
*Wide PLL Input Frequency Range
*Wide Parallel Supply Voltage Range: 1.65 to 3.6V
*Low Power Core Operation: VDDS/A=2.5 to 3.6V
*Built-in LV-CMOS Voltage Translation Capability with no External Components
*Adjustable Parallel Edge Rate
*Operates as Serializer or Deserializer
*Standby Power-Down Mode Support
*Built-in Differential Termination

*8-Bit LCD Displays for Cell Phones
*8/10-Bit Cell Phone Camera Interface
*8-Bit LCD Displays for Printers


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General Description
The XPIO™ 110GXS is a fully integrated 10 Gbps serializer/deserializer device designed for high-speed switches and routers that require very low power budget and a small footprint as well. Centering on 10 Gbps speed, the XPIO 110GXS is a versatile chip that is capable of handling applications in various standards, such as OC-192 (9.95 Gbps) and 10GE (10.31 Gbps).
An on-chip low jitter PLL generates all required clocks based on an external reference clock at 1/16 or 1/64 frequency of the serial data rate, which is 622.08 MHz or 155.52 MHz, respectively, for OC-192 applications. An Integrated Limiting Amplifier allows flexibility in placement and reduced bit-error rates (BER).
Fabricated with state-of-the-art CMOS technology, the XPIO 110GXS performs all necessary functions for serial-to-parallel and parallel-to-serial conversions, and consumes less than one third of the power consumed by the more conventional SiGe Bi-CMOS designs.

*Single chip SERDES solution with integrated transmitter and receiver
*Continuous serial operation range from 9.95 Gbps to 10.31 Gbps
*Parallel LVDS data range from 622 Mbps to 644 Mbps
*Low power consumption (800 mW typical)
*Performs 16:1 serialization and 1:16 deserialization
*Embedded Limiting Amplifier enhances receiver sensitivity
*Low-jitter PLL for clock generation
*On-chip Clock Data Recovery circuit
*On-chip FIFO to decouple transmit clocks
*Bit order swap for 10GE operations
*Programmable 4-phase LVDS clock output for easy system design
*Repeating serial data output
*Line loopback, diagnostic loopback, and simultaneous loopback modes
*Frequency Lock Alarm Output
*Programmable differential output swing on both Serial driver and Parallel LVDS driver
*1.3V core voltage and 2.5V I/O voltage
*Supports 10GE (10-Gigabit Ethernet), OC-192, XFP, XSBI and SFI-4.1 interfaces
*269-pin flip-chip BGA (15 x 15 mm body size, 0.8 mm pitch)
*-40 to 85°C operating temperature

LS110GXS-1CF269C, LS110GXS-2CF269C, LS110GXS-1CF269I

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 The GS1582 is the next generation multi-standard serializer with an integrated cable driver.
The device provides robust parallel to serial conversion, generating a SMPTE 292M/259M-C compliant serial digital output signal.
The integrated cable driver features an output disable (high impedance) mode and an adjustable signal swing.
Data input is accepted in 20-bit parallel format or 10-bit parallel format. An associated parallel clock input must be provided at the appropriate operating frequency; 74.25/74.1758/13.5MHz (20-bit mode) or 148.5/148.352/27MHz (10-bit mode).
The GS1582 features an internal PLL which, if desired, can be configured for a loop bandwidth below 100kHz.
When used in conjunction with the GO1555 Voltage Controlled Oscillator, the GS1582 can tolerate well in excess of 300ps jitter on the input PCLK and still provide output jitter within SMPTE specifications.
In addition to serializing the input, the GS1582 performs NRZ-to-NRZI encoding and scrambling as per SMPTE 292M/259M-C when operating in SMPTE mode.
When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization.
The device also provides a range of other data processing functions.
All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming.
The GS1582 can embed up to 8 channels of audio into the video data stream in accordance with SMPTE 299M and SMPTE 272M.
The audio input signal formats supported by the device include AES/EBU and I2S serial digital formats with a 16, 20 or 24 bit sample size and a 48 kHz sample rate.
Additional audio processing features include individual channel enable, channel swap, group swap, ECC generation and audio channel status insertion.
Typical power consumption, including the GO1555 VCO, is 500mW.
The standby feature allows the power to be reduced to 125mW.
Power may be reduced to less than 10mW by also removing the power to the cable driver and eliminating transitions at the parallel data and clock inputs.
The GS1582 is Pb-free and RoHS compliant.

Key Features
* HD-SDI, SD-SDI, DVB-ASI transmitter with audio embedding
* Integrated SMPTE 292M and 259M-C compliant cable driver
* Integrated ClockCleaner™
* User selectable video processing features, including:
* Generic ancillary data insertion
* Support for HVF or EIA/CEA-861 timing input
* Automatic standard detection and indication
* Enhanced SMPTE 352M payload identifier generation and insertion
* TRS, CRC, ANC data checksum, and line number calculation and insertion
* EDH packet generation and insertion
* Illegal code remapping
* SMPTE 292M and SMPTE 259M-C compliant scrambling and NRZ → NRZI encoding
* Blanking of input HANC and VANC space
* User selectable audio processing features, including:
* SMPTE 299M and SMPTE 272M-A/C compliant audio embedding
* Support for up to 8 channels
* Support for audio group replacement
* JTAG test interface
* 1.8V core and 3.3V charge pump power supply
* 1.8V and 3.3V digital I/O support
* Low power standby mode
* Operating temperature range: -20oC to +85oC
* Pb-free, RoHS compliant, 11mm x 11mm 100-ball BGA package

* SMPTE 292M and SMPTE 259M-C Serial Digital Interfaces
* DVB-ASI Serial Digital Interfaces


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 The UT54LVDS217 Serializer converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.
A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.
Every cycle of the transmit clock 21 bits of input data are sampled and transmitted.
At a transmit clock frequency of 75MHz, 21 bits of TTL data are transmitted at a rate of 525 Mbps per LVDS data channel.
Using a 75MHz clock, the data throughput is 1.575 Gbit/s (197 Mbytes/sec).
The UT54LVDS217 Serializer allows the use of wide, high speed TTL interfaces while reducing overall EMI and cable size.
All pins have Cold Spare buffers.
These buffers will be high impedance when VDD is tied to VSS.

* 15 to 75 MHz shift clock support
* Low power consumption
* Power-down mode <216μW (max)
* Cold sparing all pins
* Narrow bus reduces cable size and cost
* Up to 1.575 Gbps throughput
* Up to 197 Megabytes/sec bandwidth
* 325 mV (typ) swing LVDS devices for low EMI
* PLL requires no external components
* Rising edge strobe
* Radiation-hardened design; total dose irradiation testing to MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
* Packaging options:
- 48-lead flatpack
* Standard Microcircuit Drawing 5962-01534
- QML Q and V compliant part

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General Description
The LM2506 device adapts RGB style display interfaces to the Mobile Pixel Link (MPL) Level zero serial link. The LM2506 supports one RGB display at up to 18-bit color depth and 800 X 300 pixels (over 216 Mbps and 13.2 MHz PCLK) is supported. A mode pin configures the device as a Serializer (SER) or Deserializer (DES) so the same chip can be used on both sides of the interface.
The interconnect is reduced from 22 signals to only 3 active signals with the LM2506 chipset easing flex interconnect design, size constraints and cost.
The LM2506 in SER mode resides beside an application, graphics or baseband processor and translates a parallel bus from LVCMOS levels to serial Mobile Pixel Link levels for transmission over a flex cable (or coax) and PCB traces to the DES located near the display module.
When the Power_Down (PD*) input is asserted on the SER, the MDn and MC line drivers are powered down to save current. The DES can be controlled by a separate Power-Down input or via a signal from the SER (PDOUT*).
The LM2506 implements the physical layer of the MPL Level 0 Standard (MPL-0) and a 150 μA IB current (Class 0).

*RGB Display Interface support up to 800 x 300 1⁄2SVGA formats
*MPL-Level 0 Physical Layer using two data and one clock signal
*Low Power Consumption
*Pinout mirroring enables straight through layout with minimal vias
*Level translatio*betwee*host and display
*Auto Power Dow*o*STOP PCLK
*Link power dow*mode reduces quiescent power under < 10 μA
*1.74V to 2.0V core / analog supply voltage range
*1.74V to 3.0V I/O supply voltage range
*−30C to 85C Operating temperature range System Benefits
*Small Interface
*Low Power
*Low EMI
*Intrinsic Level Translation


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