GENERAL DESCRIPTION
The Micron® QDR™II (Quad Data Rate™) synchronous, pipelined burst SRAM employs high-speed, lowpower CMOS designs using an advanced 6T CMOS process.
The QDR architecture consists of two separate DDR (double data rate) ports to access the memory array. The read port has dedicated data outputs to support READ operations. The write port has dedicated data inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. Access to each port is accomplished using a common address bus. Addresses for reads and writes are latched on rising edges of the K and K# input clocks, respectively. Each address location is associated with two words that burst sequentially into or out of the device.
GENERAL DESCRIPTION (continued) Since data can be transferred into and out of the device on every rising edge of both clocks (K and K#, C and C#), memory bandwidth is maximized while system design is simplified by eliminating bus turnarounds.
Depth expansion is accomplished with port selects for each port (read R#, write W#), which are received at K rising edge. Port selects permit independent port operation.
All synchronous inputs pass through registers controlled by the K or K# input clock rising edges. Active LOW byte writes (BWx#) permit byte or nibble write selection. Write data and byte writes are registered on the rising edges of both K and K#. The addressing within each burst of two is fixed and sequential, beginning with the lowest and ending with the highest address. All synchronous data outputs pass through output registers controlled by the rising edges of the output clocks (C and C# if provided, otherwise K and K#).
Four balls are used to implement JTAG test capabilities: test mode select (TMS), test data-in (TDI), test clock (TCK), and test data-out (TDO). JTAG circuitry is used to serially shift data to and from the SRAM. JTAG inputs use JEDEC-standard 1.8V I/O levels to shift data during this testing mode of operation.
The SRAM operates from a +1.8V power supply, and all inputs and outputs are HSTL-compatible. The device is ideally suited for applications that benefit from a high-speed, fully-utilized DDR data bus.

FEATURES
*DLL circuitry for accurate output data placement
*Separate independent read and write data ports with concurrent transactions
*100 percent bus utilization DDR READ and WRITE operation
*Fast clock to valid data times
*Full data coherency, providing most current data
*Two-tick burst counter for low DDR transaction size
*Double data rate operation on read and write ports
*Two input clocks (K and K#) for precise DDR timing at clock rising edges only
*Two output clocks (C and C#) for precise flight time and clock skew matching—clock and data delivered together to receiving device
*Single address bus
*Simple control logic for easy depth expansion
*Internally self-timed, registered writes
*+1.8V core and HSTL I/O
*Clock-stop capability
*15mm x 17mm, 1mm pitch, 11 x 15 grid FBGA package
*User-programmable impedance output
*JTAG boundary scan

MT54W4MH9B, MT54W2MH18B, MT54W1MH36B

DESCRIPTION
The HY62U8400A is a high-speed, low power and 4M bits CMOS SRAM organized as 512K words by 8 bits. The HY62U8400A uses Hynix's high performance twin tub CMOS process technology and was designed for high-speed and low power circuit technology. It is particularly well suited for use in high-density and low power system applications. This device has a data retention mode that guarantees data to remain valid at the minimum power supply voltage of 2.0V.

FEATURES
*Fully static operation and Tri-state outputs
*TTL compatible inputs and outputs
*Low power consumption
*Battery backup(LL-part)
-2.0V(min) data retention
*Standard pin configuration
-32pin 525mil SOP
-32pin 400mil TSOP-II (Standard and Reversed)

HY62U8400A, HY62U8400A-E, HY62U8400A-I

General Description
The A63L06361 is a high-speed SRAM containing 36M bits of bit synchronous memory, organized as 1024K words by 36 bits.
The A63L06361 combines advanced synchronous peripheral circuitry, 2-bit burst control, input registers, output buffer and a 1M X 36 SRAM core to provide a wide range of data RAM applications.
The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. Synchronous inputs include all addresses (A0 - A19), all data inputs (I/O1 - I/O36 ), active LOW chip enable ( CE ), two additional chip enables (CE2, CE2 ), burst control inputs ( ADSC , ADSP , ADV ), byte write enables (BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write (GW ). Asynchronous inputs include output enable ( OE ), clock (CLK), BURST mode (MODE) and SLEEP mode (ZZ).
Burst operations can be initiated with either the address status processor ( ADSP ) or address status controller ( ADSC ) input pin. Subsequent burst sequence burst addresses can be internally generated by the A63L06361 and controlled by the burst advance ( ADV ) pin. Write cycles are internally self-timed and synchronous with the rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/O1 - I/O9, BW2 controls I/O10 - I/O18, BW3 controls I/O19 - I/O27, and BW4 controls I/O28 - I/O36, all on the condition that BWE is LOW. GW LOW causes all bytes to be written.

Features
*Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)
*Single 3.3V±5% power supply
*Synchronous burst function
*Individual Byte Write control and Global Write
*Three separate chip enables allow wide range of options for CE control, address pipelining
*Selectable BURST mode
*SLEEP mode (ZZ pin) provided
*Available in 100-pin LQFP package
*Industrial operating temperature range: -45°C to +125°C for -I series

A63L06361E-6.5, A63L06361E-6.5F, A63L06361E-7.5, A63L06361E-7.5F

General Description
The LP62S4096E-T is a low operating current 4,194,304-bit static random access memory organized as 524,288 words by 8 bits and operates on a low power supply range: 2.7V to 3.3V. It is built using AMIC's high performance CMOS process.
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures.
Two chip enable inputs are provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing.
Data retention is guaranteed at a power supply voltage as low as 2V.
*CE2 pin for CSP package only

Features
*Power supply range: 2.7V to 3.6V
*Access times: 55ns / 70ns (max.)
*Current: Very low power version: Operating: 30mA (max.), Standby: 10mA (max.)
*Full static operation, no clock or refreshing required
*All inputs and outputs are directly TTL-compatible
*Common I/O using three-state output
*Data retention voltage: 2V (min.)
*Available in 32-pin TSOP/TSSOP 36-ball CSP package

LP62S4096EV-55LLT, LP62S4096EX-55LLT, LP62S4096EU-55LLT

Description
The HM62W1400H is a 4-Mbit high speed static RAM organized 4-Mword ´ 1-bit. It has realized high speed access time by employing CMOS process (4-transistor + 2-poly resistor memory cell)and high speed circuit designing technology. It is most appropriate for the application which requires high speed and high density memory, such as cache and buffer memory in system. The HM62W1400H is packaged in 400-mil 32-pin SOJ and 400-mil 32-pin TSOP II for high density surface mounting.

Features
*Single 3.3 V supply : 3.3 V ± 0.3 V
*Access time 12/15 ns (max)
*Completely static memory
-No clock or timing strobe required
*Equal access and cycle times
*Directly TTL compatible
-All inputs and outputs
*Operating current: 180/160 mA (max)
*TTL standby current: 60/50 mA (max)
*CMOS standby current: 5 mA (max) , 1 mA (max) (L-version)
*Data retension current: 0.6 mA (max) (L-version)
*Data retension voltage: 2 V (min) (L-version)
*Center VCC and VSS type pinout

HM62W1400HJP-12, HM62W1400HJP-15, HM62W1400HLJP-12, HM62W1400HLJP-15

General Description
The DS2045 is a 1Mb reflowable nonvolatile (NV) SRAM, which consists of a static RAM (SRAM), an NV controller, and an internal rechargeable manganese lithium (ML) battery. These components are encased in a surface-mount module with a 256-ball BGA footprint. Whenever VCC is applied to the module, it recharges the ML battery, powers the SRAM from the external power source, and allows the contents of the SRAM to be modified. When VCC is powered down or out of tolerance, the controller write-protects the SRAM’s contents and powers the SRAM from the battery. Two versions of the DS2045 are available, which provide either a 5% or 10% power-monitoring trip point. The DS2045 also contains a power-supply monitor output, RST, which can be used as a CPU supervisor for a microprocessor.

Features
*Single-Piece, Reflowable, 27mm2 PBGA Package Footprint
*Internal ML Battery and Charger
*Unconditionally Write-Protects SRAM when VCC is Out-of-Tolerance
*Automatically Switches to Battery Supply when VCC Power Failures Occur
*Internal Power-Supply Monitor Detects Power Fail at 5% or 10% Below Nominal VCC (5V)
*Reset Output can be used as a CPU Supervisor for a Microprocessor
*Industrial Temperature Range (-40°C to +85°C)
*UL Recognized

Applications
*RAID Systems and Servers
*Industrial Controllers
*Gaming
*Router/Switches
*POS Terminals
*Data-Acquisition Systems
*Fire Alarms
*PLC

DS2045AB-70, DS2045AB-100, DS2045Y-70, DS2045Y-100

Functional description
The AS7C513C is a 5V high-performance CMOS 524,288-bit Static Random Access Memory (SRAM) device organized as 32,768 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for highperformance applications.
When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.
The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The AS7C513C is packaged in common industry standard packages.

Features
*Industrial (-40o to 85oC) temperature
*Organization: 32,768 words × 16 bits
*Center power and ground pins for low noise
*High speed
-12 ns address access time
-6 ns output enable access time
*Low power consumption via chip deselect
*Easy memory expansion with CE, OE inputs
*TTL-compatible, three-state I/O
*Upper and Lower byte pin
*JEDEC standard packaging
-44-pin 400 mil SOJ
-44-pin TSOP 2
*ESD protection ≥ 2000 volts

AS7C513C-12JIN, AS7C513C-12TIN

General Description
The AMIC Zero Bus Latency (ZeBLTM) SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process.
The A67L16181, A67L06361 SRAMs integrate a 2M X 18, 1M X 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. These SRAMs are optimized for 100 percent bus utilization without the insertion of any wait cycles during Write-Read alternation. The positive edge triggered single clock input (CLK) controls all synchronous inputs passing through the registers. The synchronous inputs include all address, all data inputs, active low chip enable (CE), two additional chip enables for easy depth expansion (CE2, CE2 ), cycle start input (ADV/LD ), synchronous clock enable ( CEN ), byte write enables (BW1,BW2,BW3,BW4) and read/write (R/W).
Asynchronous inputs include the output enable (OE), clock (CLK), SLEEP mode (ZZ, tied LOW if unused) and burst mode (MODE). Burst Mode can provide either interleaved or linear operation, burst operation can be initiated by synchronous address Advance/Load (ADV/LD ) pin in Low state. Subsequent burst address can be internally generated by the chip and controlled by the same input pin ADV/LD in High state.
Write cycles are internally self-time and synchronous with the rising edge of the clock input and when R/W is Low. The feature simplified the write interface. Individual Byte enables allow individual bytes to be written. BW1 controls I/Oa pins; BW2 controls I/Ob pins; BW3 controls I/Oc pins; and BW4 controls I/Od pins. Cycle types can only be defined when an address is loaded.
The SRAM operates from a +3.3V power supply, and all inputs and outputs are LVTTL-compatible. The device is ideally suited for high bandwidth utilization systems.

Features
*Fast access time: 6.5/7.5/8.5 ns (153, 133, 117 MHz)
*Zero Bus Latency between READ and WRITE cycles allows 100% bus utilization
*Signal +3.3V ± 5% power supply
*Individual Byte Write control capability
*Clock enable ( CEN) pin to enable clock and suspend operations
*Clock-controlled and registered address, data and control signals
*Registered output for pipelined applications
*Three separate chip enables allow wide range of options for CE control, address pipelining
*Internally self-timed write cycle
*Selectable BURST mode (Linear or Interleaved)
*SLEEP mode (ZZ pin) provided
*Available in 100 pin LQFP package

A67L06361, A67L16181E-6.5, A67L16181E-7.5, A67L16181-8.5

Functional description
The AS7C256B is a 5V high-performance CMOS 262,144-bit Static Random-Access Memory (SRAM) device organized as 32,768 words × 8 bits. It is designed for memory applications requiring fast data access at low voltage, including PentiumTM, PowerPCTM, and portable computing. Alliance’s advanced circuit design and process techniques permit 5.0V operation
without sacrificing performance or operating margins.
The device enters standby mode when CE is high. Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high-performance applications. The chip enable (CE) input permits easy memory expansion with multiple-bank memory organizations.
A write cycle is accomplished by asserting chip enable (CE) and write enable (WE) LOW. Data on the input pins I/O0-I/O7 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting chip enable (CE) and output enable (OE) LOW, with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When chip enable or output enable is high, or write enable is low, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible. Operation is from a single 5.0±0.5V supply. The AS7C256B is packaged in high volume industry standard packages.

Features
*Industrial (-40o to 85oC) temperature
*Organization: 32,768 words × 8 bits
*High speed
-12 ns address access time
-6 ns output enable access time
*Low power consumption via chip deselect
*One chip select plus one Output Enable pin
*Bidirectional data inputs and outputs
*TTL-compatible
*28-pin JEDEC standard packages
-300 mil SOJ
-8 × 13.4 mm TSOP
-300 mil PDIP
*ESD protection ≥ 2000 volts

AS7C256B-12PIN, AS7C256B-12JIN, AS7C256B-12TIN

GENERAL DESCRIPTION
The Micron® SyncBurst™ SRAM family employs high-speed, low-power CMOS designs that are fabricated using an advanced CMOS process.
Micron’s 8Mb SyncBurst SRAMs integrate a 512K x 18, 256K x 32, or 256K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE#), two additional chip enables for easy depth expansion CE2#, CE2), burst control inputs (ADSC#, ADSP#,ADV#), byte write enables (BWx#) and global write (GW#). Note that CE2# is not available on the T Version.
Asynchronous inputs include the output enable (OE#), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. The data-out (Q), enabled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from one to four bytes wide (x32/x36), as controlled by the write control inputs.
Burst operation can be initiated with either address status processor (ADSP#) or address status controller (ADSC#) inputs. Subsequent burst addresses can be internally generated as controlled by the burst advance input (ADV#).
Address and write control are registered on-chip to simplify WRITE cycles. This allows self-timed WRITE cycles. Individual byte enables allow individual bytes to be written. During WRITE cycles on the x18 device, BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb. During WRITE cycles on the x32 and x36 devices, BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc; BWd# controls DQd’s and DQPd. GW# LOW causes all bytes to be written. Parity bits are only available on the x18 and x36 versions.
Micron’s 8Mb SyncBurst SRAMs operate from a +3.3V VDD power supply, and all inputs and outputs are TTL-compatible. Users can choose either a 3.3V or 2.5V I/O version. The device is ideally suited for 486, Pentium®, 680x0 and PowerPC systems and those systems that benefit from a wide synchronous data bus.
The device is also ideal in generic 16-, 18-, 32-, 36-, 64-, and 72-bit-wide applications.

FEATURES
*Fast clock and OE# access times
*Single +3.3V +0.3V/-0.165V power supply (VDD)
*Separate +3.3V or +2.5V isolated output buffer supply (VDDQ)
*SNOOZE MODE for reduced-power standby
*Common data inputs and data outputs
*Individual BYTE WRITE control and GLOBAL WRITE
*Three chip enables for simple depth expansion and address pipelining
*Clock-controlled and registered addresses, data I/Os and control signals
*Internally self-timed WRITE cycle
*Burst control (interleaved or linear burst)
*Automatic power-down for portable applications
*100-pin TQFP package
*165-pin FBGA
*Low capacitive bus loading
*x18, x32, and x36 versions available

MT58L512L18F, MT58L256L32F, MT58L256L36F, MT58L512V18F, MT58L256V32F