Description
The ZL30402 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for ST-BUS and GCI backplanes.
The ZL30402 operates in NORMAL (LOCKED), HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30402 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation.
The ZL30402 operates from a single 3.3 V power supply and offers a 5 V tolerant microprocessor interface.

Features
*Meets requirements of GR-253 for SONET stratum 3 and SONET Minimum Clocks (SMC)
*Meets requirements of GR-1244 for stratum 3
*Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks (SEC)
*Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E2, E3, STM-1 and 19.44 MHz
*Holdover accuracy to 1x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements
*Continuously monitors Primary and Secondary reference clocks
*Provides “hit-less” reference switching
*Compensates for Master Clock Oscillator accuracy
*Detects frequency of both reference clocks and synchronizes to any combination of 8 kHz,
1.544 MHz, 2.048 MHz and 19.44 MHz reference frequencies.
*Allows Hardware or Microprocessor control
*Pin compatible with MT90401 device.

Applications
*Synchronization for SDH and SONET Network Elements
*Clock generation for ST-BUS and GCI backplanes

ZL30402/QCC, ZL30402QCC1
TAG PLL, SONET/SDH

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Description
The Si5100 is a complete low-power transceiver for high-speed serial communication systems operating between OC-48 and 2.7 Gbps.
The receive path consists of a fully-integrated limiting amplifier, clock and data recovery unit
(CDR), and 1:16 deserializer.
The transmit path combines a low-jitter clock multiplier unit (CMU) with a 16:1 serializer.
The CMU uses Silicon Laboratories’ DSPLL technology to provide superior jitter performance while reducing design complexity by eliminating external loop filter components.
To simplify BER optimization in long-haul applications, programmable slicing and sample phase
adjustment are supported.
The Si5100 operates from a single 1.8 V supply over the industrial temperature range (–20 to 85 °C).

Features
Complete, low-power, high-speed, SONET/SDH transceiver with integrated limiting amp, CDR, CMU, and MUX/DEMUX
* Data rates supported: OC-48/STM-16 through 2.7 Gbps FEC
* Low-power operation 1.2 W (typ)
* DSPLL™ based clock multiplier unit w/ selectable loop filter bandwidths
* Integrated limiting amplifier
* Loss-of-signal (LOS) alarm
* Diagnostic and line loopbacks
* SONET-compliant loop timed operation
* Programmable slicing level and sample phase adjustment
* LVDS/LVPECL compatible interface
* Single supply 1.8 V operation
* 15 x 15 mm BGA package

Applications
* SONET/SDH transmission systems
* Optical transceiver modules
* SONET/SDH test equipment

SI5100-F-BC

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