Description
Pericom Semiconductor’s PI3HDMI series of switch circuits are targeted for high-resolution video networks that are based on DVI/HDMI standards, and TMDS signal processing. The
PI3HDMI412FT-B is an 8- to 4-Channel Mux/DeMux Switch. The device multiplexes differential signals to one of two corresponding outputs. The switch is bidirectional and offers little or no attenuation of the high-speed signals at the outputs. It is designed for low bit-to-bit skew and high channel-to-channel noise isolation.
The allowable data rate of 5.0Gbps provides the resolution required by the next generation HDTV and PC graphics. Three differential channels are used for data (video signals for DVI or audio/video signals for HDMI), and one differential channel is used for Clock for decoding the TMDS signals at the outputs.
Due to its integrated pull-up resistors, the product has been designed specifi cally for applications where the part is used as a 2 to 1 mux, not 1 to 2 demux. Therefore, Pericom only recommends the part to be used as a 2 to 1 mux when dealing with HDMI signals. Even though the passive circuitry does not eliminate the bi-directional functionality, it is not ideal when used with HDMI signals. If DVI are used, either direction can be used.

Features
*4-Differential Channel 2:1 Mux/DeMux
*HDMI 1.1, 1.2, and 1.3 compatible
*Allowable Data Rate: > 5.0 Gbps
*Supports both AC coupled and DC coupled signals
*Switching speed: 4ns
*Isolation: -40dB @ 2.0 Gbps
*Crosstalk: -31dB @ 2.0 Gbps
*ESD: Data bits @ 8kV contact, select bit @ 2kV HBM
*Low bit-to-bit skew
*Enable/Disable Time: 9ns
*Bidirectional
*Packaging (Pb-free & Green):
— 42-pin TQFN (ZH42)
— 48-pin BQSOP (B48)

PI3HDMI412FT-BZHE
PI3HDMI412FT-BBE

Outline
 This IC is a video signal driver IC that supports 3-ch interlace video developed for DVD players.
It includes a low-pass filter that attenuates the noise element during DA conversion, and a 3-channel 6dB amp with 75Ω driver.
In addition, external ESD protection diodes can be reduced by a sag correction pin for reducing output coupling capacitance, and enhancement ot the ESD protection elements for the output pins.

Features
* Includes a SAG correction pin.
* Enabled to drive a 3-channel 6dB amp with 75Ω driver
* Includes a 4th-order low-pass filter Frequency response: 6.75MHz ± 1dB / 27MHz – 27dB min.
* Includes a 6dB amp
* Includes a power save function
* S/N=80dB typ. (Y/C mix:74dB typ.)
* ESD strengh (aerial discharge) of ±15kV (IEC standard)
* Includes mode select pins which correspond to various video signals

Applications
* DVD players
* Digital STB
* Other digital video equipment

description
The TMS320C30 is the newest member of the TMS320C3x generation of DSPs from Texas Instruments (TIE).
The TMS320C30 is a 32-bit floating-point processor manufactured in 0.7-mm triple-level-metal CMOS technology.
The TMS320C30’s internal busing and special DSP instruction set have the speed and flexibility to execute up to 50 MFLOPS (million floating-point operations per second).
The TMS320C30 optimizes speed by implementing functions in hardware that other processors implement through software or microcode.
This hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320C30 can perform parallel multiply and ALU operations on integer or floating-point data in a single cycle.
Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs, internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.
High performance and ease of use are results of these features.
General-purpose applications are enhanced greatly by the large address space, multiprocessor interface, internally and externally generated wait states, two external interface ports, two timers, serial ports, and multiple interrupt structure. The TMS320C30 supports a wide variety of system applications from host processor to dedicated coprocessor.

* High-Performance Floating-Point Digital
Signal Processor (DSP)
- TMS320C30-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
- TMS320C30-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
- TMS320C30-33 (5 V)
60-ns Instruction Cycle Time
183.3 MOPS, 33.3 MFLOPS, 16.7 MIPS
- TMS320C30-27 (5 V)
74-ns Instruction Cycle Time
148.5 MOPS, 27 MFLOPS, 13.5 MIPS
* 32-Bit High-Performance CPU
* 16-/32-Bit Integer and 32-/40-Bit Floating-Point Operations
* 32-Bit Instruction Word, 24-Bit Addresses
* Two 1K × 32-Bit Single-Cycle Dual-Access On-Chip RAM Blocks
* One 4K × 32-Bit Single-Cycle Dual-Access On-Chip ROM Block
* On-Chip Memory-Mapped Peripherals:
- Two Serial Ports
- Two 32-Bit Timers
- One-Channel Direct Memory Access (DMA) Coprocessor for Concurrent I/O and CPU Operation
* Two 32-Bit External Ports
* 24- and 13-Bit Addresses
* 0.7-mm Enhanced Performance Implanted CMOS (EPICE) Technology
* 208-Pin Plastic Quad Flat Package (PPM Suffix)
* 181-Pin Grid Array Ceramic Package (GEL Suffix)
* Eight Extended-Precision Registers
* Two Address Generators With Eight Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
* Two- and Three-Operand Instructions
* Parallel Arithmetic and Logic Unit (ALU) and Multiplier Execution in a Single Cycle
* Block-Repeat Capability
* Zero-Overhead Loops With Single-Cycle Branches
* Conditional Calls and Returns
* Interlocked Instructions for Multiprocessing Support
* Two Sets of Memory Strobes (STRB and MSTRB) and One I/O Strobe (IOSTRB)
* Separate Bus-Control Registers for Each Strobe-Control Wait-State Generation

TMS320C30GEL27

Features
• Digital compensation of sensor offset, sensitivity, temperature drift and non-linearity
• Accommodates differential sensor signal spans from 1.2mV/V to 60mV/V
• ZACwireTM one-wire interface.
• Internal temperature compensation and detection via bandgap PTAT*
• Optional sequential output of both temperature and bridge readings on ZACwireTM digital output
• Output options: rail-to-rail analog output voltage, absolute analog voltage, digital one-wire-interface
• Supply voltage 2.7 to 5.5V, with external JFET 5.5V to 30V
• Current consumption, depending on adjusted sample rate: 0.25mA to 1mA
• Wide operational temperature: –50 to +150°C
• Fast response time 1ms(typical)
• High voltage protection up to 30V with external JFET
• Chopper-stabilized true differential ADC
• Buffered and chopper-stabilized output DAC
* Proportional to absolute temperature

Benefits
• No external trimming components required
• PC-controlled configuration and calibration via onewire interface – simple, low cost
• High accuracy (±0.1% FSO @ -25 to 85°C; ±0.25% FSO @ -40 to 125°C)
• Single pass calibration – quick and precise
• Suitable for battery-powered applications
• Small SOP8 package

Brief Description
The RBicLite™ is a CMOS integrated circuit, which enables easy and precise calibration of resistive bridge sensors via EEPROM. When mated to a resistive bridge sensor, it will digitally correct offset and gain with the option to correct offset and gain coefficients and linearity over temperature. A second order compensation can be enabled for temperature coefficients of gain and offset or bridge linearity.
RBicLite™ communicates via ZMD’s ZACwireTM serial interface to the host computer and is easily mass calibrated in a Windows® environment. Once calibrated, the output SIG™ pin can provide selectable 0 to 1V, rail-to-rail ratiometric analog output, or digital serial output of bridge data with optional temperature data.
• Development Kit available
• Multi-Unit Calibrator Kit available
• Support for industrial mass calibration available
• Quick circuit customization possible for large production volumes

Description
The NTE1863 is a single−chip integrated circuit in a 42−Lead DIP type package and incorporates a circuit to process all types of signals (VIF, SIF, video, chroma, deflection) for color TVs based on the NTSC system. In designing this device, its basic characteristics including synchronization performance are greatly improved, and taking into consideration its needed application in AV equipment such as VCRs, the necessity of adjustment is substantially reduced. A simple, compact color TV can be implemented by simply connecting a tuner, power supply, and output circuit to the NTE1863.
When using the NTE1863 in conjunction with vertical output−use IC NTE1855, only one connection (vertical timing pulse) is required, with no connection required for feedback, thus simplifying layout of printed circuit pattern.

Features
*Small−sized Package
*Minimum Number of External Parts Required VIF−SIF
*Excellent Buzz Beat Characteristics
*High−Gain VIF Amplifier Eliminating the need for a Preamplifier
*AGC Speed can be Increased
*Video/Audio Simultaneous Muting, or Audio−Only Muting Possible Video−Chroma
*A Quadratic Differentiation Circuit allowing Soft Video Tone Operation is also Incorporated
*Adjustment−free Chroma Sync

Deflection
*Adjustment−free Horizontal, Vertical Sync
*Dual AFC System with Excellent Horizontal Noise Characteristics
*Vertical Sync Stabilizing Circuit which is Scarcely Affected by Motor Noise

High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• Flexible addressing modes
• 84 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Up to 144 Kbytes on-chip Flash program space
• Up to 48K instruction words
• Up to 8 Kbytes of on-chip data RAM
• Up to 4 Kbytes of nonvolatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPs operation:
- DC to 40 MHz external clock input
- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x)
• Up to 41 interrupt sources:
- 8 user selectable priority levels
- 5 external interrupt sources
- 4 processor traps

DSP Features:
• Dual data fetch
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier
• All DSP instructions are single cycle
- Multiply-Accumulate (MAC) operation
• Single-cycle ±16 shift

Peripheral Features:
• High-current sink/source I/O pins: 25 mA/25 mA
• Five 16-bit timers/counters; optionally pair up 16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions:
• Data Converter Interface (DCI) supports common audio Codec protocols, including I2S and AC’97
• 3-wire SPI™ modules (supports 4 Frame modes)
• I2C™ module supports Multi-Master/Slave mode and 7-bit/10-bit addressing
• Two addressable UART modules with FIFO buffers
• Two CAN bus modules compliant with CAN 2.0B standard

Analog Features:
• 12-bit Analog-to-Digital Converter (ADC) with:
- 200 Ksps conversion rate
- Up to 16 input channels
- Conversion available during Sleep and Idle
• Programmable Low-Voltage Detection (PLVD)
• Programmable Brown-out Detection and Reset generation

Special Microcontroller Features:
• Enhanced Flash program memory:
- 10,000 erase/write cycle (min.) for industrial temperature range, 100K (typical)
• Data EEPROM memory:
- 100,000 erase/write cycle (min.) for industrial temperature range, 1M (typical)
• Self-reprogrammable under software control
• Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST)
• Flexible Watchdog Timer (WDT) with on-chip low-power RC oscillator for reliable operation

dsPIC30F6011A
dsPIC30F6012A
dsPIC30F6013A
dsPIC30F6014A

* Low Supply-Voltage Range, 1.8 V to 3.6 V
* Ultralow-Power Consumption:
-- Active Mode: 270 μA at 1 MHz, 2.2 V
-- Standby Mode: 0.7 μA
-- Off Mode (RAM Retention): 0.1 μA
* Ultrafast Wake-Up From Standby Mode in Less Than 1 μs
* 16-Bit RISC Architecture, 62.5 ns Instruction Cycle Time
* Hardware Multiplier
* Basic Clock Module Configurations:
-- Internal Frequencies up to 16MHz With
Four Calibrated Frequencies to ±1%
-- Internal Very Low Power LF Oscillator
-- 32-kHz Crystal
-- High-Frequency Crystal up to 16 MHz
-- Resonator
-- External Digital Clock Source
-- External Resistor
* 16-Bit Timer_A With Three Capture/Compare Registers
* 16-Bit Timer_B With Three Capture/Compare Registers
* On-Chip Comparator for Analog Signal Compare Function or Slope A/D Conversion
* Universal Serial Communication Interface
-- Enhanced UART Supporting Auto
Baudrate Detection (LIN)
-- IrDA Encoder and Decoder
-- Synchronous SPI
-- I2Ct
* Brownout Detector
* Serial Onboard Programming, No External Programming Voltage Needed Programmable Code Protection by Security Fuse
* Bootstrap Loader in Flash Devices
* On-Chip Emulation Module
* Family Members Include:
MSP430F2330 8KB + 256B Flash Memory 1KB RAM
MSP430F2350 16KB + 256B Flash Memory 2KB RAM
MSP430F2370 32KB + 256B Flash Memory 2KB RAM
* Available in 40-pin QFN Package
* For Complete Module Descriptions, See the MSP430x2xx Family User’s Guide

description
 The Texas InstrumentsMSP430 family of ultralow-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes is optimized to achieve extended battery life in portablemeasurement applications.
 The devices feature a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 μs.
 The MSP430F23x0 series is an ultralow-power microcontroller with two built-in 16-bit timers, one universal serial communication interface (USCI), a versatile analog comparator, and 32 I/O pins.

MSP430F2330IRHA
MSP430F2350IRHA
MSP430F2370IRHA
MSP430F2330TRHA
MSP430F2350TRHA
MSP430F2370TRHA

FEATURES
* Low cost, 3.3 V CMOS MxFE® for broadband modems
* 10-bit digital-to-analog converter (DAC)
- 2×/4× interpolation filter
- 250 MSPS DAC update rate
* 10-bit, 75 MSPS ADC
* Low noise RxPGA
- Dual channel muxed input
- 6 dB input overload attenuator
−12 dB to +48 dB (without attenuator)
* Third-order programmable low-pass filter
* Flexible digital datapath interface
- Half-duplex and full-duplex operation
- Programmable delay Tx driver disable signal
* Various power-down/reduction modes
* Internal clock multiplier (PLL)
* 2 auxiliary programmable clock outputs
* 64-lead LFCSP

APPLICATIONS
Power-line networking

GENERAL DESCRIPTION
 The AD9867 is a mixed-signal front-end (MxFE) IC for transceiver applications requiring Tx and Rx path functionality with data rates up to 75 MSPS. Its flexible digital interface, power-saving modes, and high Tx-to-Rx isolation make the part well suited for half-duplex and full-duplex applications. The digital interface is extremely flexible allowing simple interfaces to digital back ends. Power-saving modes can reduce power consumption of individual functional blocks or can power down unused blocks in half-duplex applications.

 A serial port interface (SPI®) allows software programming of the various functional blocks. An on-chip PLL clock multiplier and synthesizer provide all the required internal clocks, as well as two external clocks from a single crystal or clock source.

 The Tx signal path consists of a bypassable 2×/4× low-pass interpolation filter and a 10-bit, 250 MSPS TxDAC. The transmit path signal bandwidth can be as high as 33.6 MHz at an input data rate of 75 MSPS. The TxDAC provides differential current outputs that can be steered directly to a differential or single-ended external load. Tx power can be digitally controlled over a 7.5 dB range in 0.5 dB steps.

The receive path consists of a programmable amplifier (RxPGA), a tunable low-pass filter (LPF), and a 10-bit analog-to-digital converter (ADC). The low noise RxPGA has a programmable gain range of −12 dB to +48 dB in 1 dB steps. Its input referred noise is less than 3.6 nV/√Hz for gain settings beyond 36 dB. An optional attenuator provides an additional 6 dB (or more) of attenuation (when combined with external series resistors).
 
 The receive path LPF cutoff frequency can either be set over a 22 MHz to 38 MHz range or simply bypassed. The 10-bit ADC achieves excellent dynamic performance over a 5 MSPS to 75 MSPS span. Both the RxPGA and the ADC offer scalable power consumption allowing power/performance optimization.
 The AD9867 provides a highly integrated solution for broadband modems. It is available in a space-saving, 64-lead LFCSP and is specified over the commercial (−40°C to +85°C) temperature range.

FEATURES
- 12 MSPS Correlated Double Sampler (CDS)
- 10-Bit 12 MHz A/D Converter
- No Missing Codes Guaranteed
- 6 dB to 40 dB Variable Gain Amplifier (VGA)
- Black Level Clamp with Variable Level Control
- Complete On-Chip Timing Generator
- Precision Timing Core with 1.7 ns Resolution
- On-Chip: 6-Channel Horizontal and 1-Channel RS Drivers
- 4-Phase Vertical Transfer Clocks
- Electronic and Mechanical Shutter Modes
- On-Chip Sync Generator with External Sync Option

APPLICATIONS
- Digital Still Cameras
- Industrial Imaging

GENERAL DESCRIPTION
The AD9937 is a highly integrated CCD signal processor. It includes a complete analog front end with A/D conversion, combined with a full-function programmable timing generator.
A Precision Timing core allows adjustment of high speed clocks with 1.7 ns resolution at 12 MHz operation.

 The AD9937 is specified at pixel rates of up to 12 MHz. The analog front end includes black level clamping, CDS, VGA, and a 10-bit A/D converter. The timing generator provides all the
necessary CCD clocks: RS, H-clocks, V-clocks, sensor gate pulses, and substrate charge reset pulse. Operation is programmed using a 3-wire serial interface.
The AD9937 is packaged in a 56-lead LFCSP and specified over an operating temperature range of –25°C to +85°C.

AD9937KCP
AD9937KCPRL

FEATURES

New AD9949A supports CCD line length > 4096 pixels
Correlated double sampler (CDS)
0 dB to 18 dB pixel gain amplifier (PxGA®)
6 dB to 42 dB 10-bit variable gain amplifier (VGA)
12-bit, 36 MSPS analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing driver
Precision Timing™ core with < 600 ps resolution
On-chip 3 V horizontal and RG drivers
40-lead LFCSP package

APPLICATIONS
Digital still cameras
High speed digital imaging applications

GENERAL DESCRIPTION
 The AD9949 is a highly integrated CCD signal processor for digital still camera applications. Specified at pixel rates of up to 36 MHz, the AD9949 consists of a complete analog front end with A/D conversion, combined with a programmable timing driver. The Precision Timing core allows adjustment of high speed clocks with < 600 ps resolution.

 The analog front end includes black level clamping, CDS, PxGA, VGA, and a 36 MSPS, 12-bit ADC. The timing driver provides the high speed CCD clock drivers for RG and H1 to H4. Operation is programmed using a 3-wire serial interface.
 
 Packaged in a space-saving, 40-lead LFCSP package, the AD9949 is specified over an operating temperature range of 20°C to +85°C.