DESCRIPTION
The Hynix HY5DU283222Q is a 134,217,728-bit CMOS Double Data Rate(DDR) Synchronous DRAM, ideally suited for the point-to-point applications which requires high bandwidth.
The Hynix 4Mx32 DDR SDRAMs offer fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All input and output voltage levels are compatible with SSTL_2.

FEATURES
*VDD, VDDQ = 2.5V ± 5%
*All inputs and outputs are compatible with SSTL_2 interface
*JEDEC standard 20mm x 14mm 100pin LQFP with 0.65mm pin pitch
*Fully differential clock inputs (CK, /CK) operation
*Double data rate interface
*Source synchronous - data transaction aligned to bidirectional data strobe (DQS)
*Data outputs on DQS edges when read (edged DQ) Data inputs on DQS centers when write (centered DQ)
*Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe
*All addresses and control inputs except Data, Data strobes and Data masks latched on the rising edges of the clock
*Write mask byte controls by DM (DM0 ~ DM3)
*Programmable /CAS Latency 3 and 4 supported
*Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode
*Internal 4 bank operations with single pulsed /RAS
*tRAS Lock-Out function supported
*Auto refresh and self refresh supported
*4096 refresh cycles / 32ms
*Half strength and Matched Impedance driver option controlled by EMRS

HY5DU283222Q-4, HY5DU283222Q-45, HY5DU283222Q-5, HY5DU283222Q-55

GENERAL DESCRIPTION
The K4M56163PG is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

FEATURES
*1.8V power supply.
*LVCMOS compatible with multiplexed address.
*Four banks operation.
*MRS cycle with address key programs.
-CAS latency (1, 2 & 3).
-Burst length (1, 2, 4, 8 & Full page).
-Burst type (Sequential & Interleave).
*EMRS cycle with address key programs.
*All inputs are sampled at the positive going edge of the system clock.
*Burst read single-bit write operation.
*Special Function Support.
-PASR (Partial Array Self Refresh).
-Internal TCSR (Temperature Compensated Self Refresh)
-DS (Driver Strength)
-DPD (Deep Power Down)
*DQM for masking.
*Auto refresh.
*64ms refresh period (8K cycle)
*Commercial Temperature Operation (-25°C ~ 70°C).
*Extended Temperature Operation (-25°C ~ 85°C).
*54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free).

K4M56163PG-RE75, K4M56163PG-BE75, K4M56163PG-RG75

General Description
The 1Gb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 1,073,741,824 bits. It is internally configured as a quadbank DRAM.
The 1Gb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 1Gb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte.
The 1Gb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command
are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access.
The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst access.
As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time.
An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive option outputs are SSTL_2, Class II compatible.

Features
*VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
*Bidirectional data strobe (DQS) transmitted/received with data, i.e., source-synchronous data capture (x16 has two – one per byte)
*Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle
*Differential clock inputs (CK and CK#)
*Commands entered on each positive CK edge
*DQS edge-aligned with data for READs; centeraligned with data for WRITEs
*DLL to align DQ and DQS transitions with CK
*Four internal banks for concurrent operation
*Data mask (DM) for masking write data (x16 has two–one per byte)
*Programmable burst lengths: 2, 4, or 8
*Auto Refresh and Self Refresh Modes
*Longer lead TSOP for improved reliability (OCPL)
*2.5V I/O (SSTL_2 compatible)
*Concurrent auto precharge option is supported
*tRAS lockout supported (tRAP = tRCD)

MT46V128M8, MT46V64M16

Description
The EBE21RD4ABHA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM with sFBGA stacking technology. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each SDRAM on the module board.

Features
*240-pin socket type dual in line memory module (DIMM)
-PCB height: 30.0mm
-Lead pitch: 1.0mm
-Lead-free
*1.8V power supply
*Data rate: 533Mbps/400Mbps (max.)
*1.8 V (SSTL_18 compatible) I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in
capturing data at the receiver
*DQS is edge aligned with data for READs; center aligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data referenced to both edges of DQS
*Four internal banks for concurrent operation (Components)
*Burst length: 4, 8
*/CAS latency (CL): 3, 4, 5
*Auto precharge option for each burst access
*Auto refresh and self refresh modes
*7.8μs average periodic refresh interval
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation
*1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)

EBE21RD4ABHA-5C-E, EBE21RD4ABHA-4A-E

DESCRIPTION
Maxwell Technologies’ Synchronous Dynamic Random Access Memory (SDRAM) is ideally suited for space applications requiring high performance computing and high density memory storage. As microprocessors increase in speed and demand for higher density memory escalates, SDRAM has proven to be the ultimate solution by providing bit-counts up to 1.25 Gigabits and speeds up to 100 Megahertz. SDRAMs represent a significant advantage in memory technology over traditional DRAMs including the ability to burst data synchronously at high rates with automatic column-address generation, the ability to interleave between banks masking precharge time
Maxwell Technologies’ patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding for a lifetime in orbit or space mission. In a typical GEO orbit, RAD-PAK® provides greater than 100 krads(Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defined Class K.

FEATURES
*1.25 Gigabit ( 8-Meg X 40-Bit X 4-Banks)
*RAD-PAK® radiation-hardened against natural space radiation
*Total Dose Hardness: >100 krad (Si), depending upon space mission
*Excellent Single Event Effects: SELTH > 85 MeV/mg/cm2 @ 25°C
*JEDEC Standard 3.3V Power Supply
*Clock Frequency: 100 MHz Operation
*Operating tremperature: -55 to +125 °C
*Auto Refresh
*Single pulsed RAS
*2 Burst Sequence variations Sequential (BL =1/2/4/8) Interleave (BL = 1/2/4/8)
*Programmable CAS latency: 2/3
*Power Down and Clock Suspend Modes
*LVTTL Compatible Inputs and Outputs
*Package: 132 Lead Quad Stack Pack Flat Package

97SD3240RPQK, 97SD3240RPQH, 97SD3240RPQI, 97SD3240RPQE

Description
All inputs and outputs are referred to the rising edge of the clock input. The HM5216165 is offered in 2 banks for improved performance.

Features
*3.3 V Power supply
*Clock frequency: 100 MHz/83 MHz
*LVTTL interface
*Single pulsed RAS
*2 Banks can operates simultaneously and independently
*Burst read/write operation and burst read/single write operation capability
*Programmable burst length: 1/2/4/8/full page
*2 variations of burst sequence
-Sequential (BL = 1/2/4/8/full page)
-Interleave (BL = 1/2/4/8)
*Programmable CAS latency: 1/2/3
*Byte control by DQMU and DQML
*Refresh cycles: 4096 refresh cycles/64 ms
*2 variations of refresh
-Auto refresh
-Self refresh

HM5216165TT-10H, HM5216165TT-12

DESCRIPTION
Maxwell Technologies’ Synchronous Dynamic Random Access Memory (SDRAM) is ideally suited for space applications requiring high performance computing and high density memory storage. As microprocessors increase in speed and demand for higher density memory escalates, SDRAM has proven to be the ultimate solution by providing bit-counts up to 1.5 Gigabits and speeds up to 100 Megahertz. SDRAMs represent a significant advantage in memory technology over traditional DRAMs including the ability to burst data synchronously
at high rates with automatic column-address generation, the ability to interleave between banks masking precharge time
Maxwell Technologies’ patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding for a lifetime in orbit or space mission. In a typical GEO orbit, RAD-PAK® provides greater than 100 krads(Si)
radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defined Class K.

FEATURES
• 1.5 Giggabit ( 8-Meg X 48-Bit X 4-Banks)
• RAD-PAK® radiation-hardened against natural space radiation
• Total Dose Hardness: >100 krad (Si), depending upon space mission
• Excellent Single Event Effects: SELTH > 85 MeV/mg/cm2 @ 25°C
• JEDEC Standard 3.3V Power Supply
• Clock Frequency: 100 MHz Operation
• Operating tremperature: -55 to +125 °C
• Auto Refresh
• Single pulsed RAS
• 2 Burst Sequence variations Sequential (BL =1/2/4/8) Interleave (BL = 1/2/4/8)
• Programmable CAS latency: 2/3
• Power Down and Clock Suspend Modes
• LVTTL Compatible Inputs and Outputs
• Package: 132 Lead Quad Stack Pack Flat Package

97SD3248RPQH, 97SD3248RPQK, 97SD3248RPQI, 97SD3248RPQE

Description
The EM44AM1684LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 512Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (12.5mmx10mm, 0.8mm x 0.8mm ball pitch).

Features
*JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
*All inputs and outputs are compatible with SSTL_18 interface.
*Fully differential clock inputs (CK,/CK) operation.
*4 Banks
*Posted CAS
*Burst Length: 4 and 8.
*Programmable CAS Latency (CL): 3, 4 and 5.
*Programmable Additive Latency (AL): 0, 1, 2, 3 and 4.
*Write Latency (WL) =Read Latency (RL) -1.
*Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
*Bi-directional Differential Data Strobe (DQS).
*Data inputs on DQS centers when write.
*Data outputs on DQS, /DQS edges when read.
*On chip DLL align DQ, DQS and /DQS transition with CK transition.
*DM mask write data-in at the both rising and falling edges of the data strobe.
*Sequential & Interleaved Burst type available.
*Off-Chip Driver (OCD) Impedance Adjustment
*On Die Termination (ODT)
*Auto Refresh and Self Refresh
*8,192 Refresh Cycles / 64ms
*Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≦ 95°C
*RoHS Compliance
*Partial Array Self-Refresh (PASR)
*High Temperature Self-Refresh rate enable

EM44AM1684LBA-5F, EM44AM1684LBA-37F, EM44AM1684LBA-3F

Description
The EBE51UD8AEFA is 64M words × 64 bits, 1 rank DDR2 SDRAM unbuffered module, mounting 8 pieces of 512M bits DDR2 SDRAM sealed in FBGA (μBGA) package. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4 bits prefetchpipelined architecture. Data strobe (DQS and /DQS)
both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each FBGA (μBGA) on the module board.

Features
*240-pin socket type dual in line memory module (DIMM)
- PCB height: 30.0mm
- Lead pitch: 1.0mm
- Lead-free
*Power supply: VDD = 1.8V ± 0.1V
*Data rate: 667Mbps (max.)
*SSTL_18 compatible I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, differential data strobe (DQS and /DQS) is transmitted/received with data, to be used capturing data at the receiver
*DQS is edge aligned with data for READs: centeraligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge: data and data mask referenced to both edges of DQS
*Four internal banks for concurrent operation (components)
*Data mask (DM) for write data
*Burst lengths: 4, 8
*/CAS Latency (CL): 3, 4, 5
*Auto precharge operation for each burst access
*Auto refresh and self refresh modes
*Average refresh period
- 7.8μs at 0°C ≤ TC ≤ +85°C
- 3.9μs at +85°C < TC ≤ +95°C
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation

EBE51UD8AEFA-6E-E

GENERAL DESCRIPTION
The K4S561632C is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

FEATURES
*JEDEC standard 3.3V power supply
*LVTTL compatible with multiplexed address
*Four banks operation
*MRS cycle with address key programs
 -CAS latency (2 & 3)
 -Burst length (1, 2, 4, 8 & Full page)
 -Burst type (Sequential & Interleave)
*All inputs are sampled at the positive going edge of the system clock.
*Burst read single-bit write operation
*DQM for masking
*Auto & self refresh
*64ms refresh period (8K Cycle)

K4S561632C-TC/L60, K4S561632C-TC/L7C, K4S561632C-TC/L75