'SDI' related articles 2

  1. 2009/10/07 GS9068 - SD SDI Cable Driver
  2. 2008/07/19 GS9090B - 270Mb/s Deserializer for SDI
The GS9068 is a second generation high-speed bipolar integrated circuit designed to drive one or two 75Ω co-axial cables at data rates up to 540Mb/s.
The GS9068 accepts a LVPECL level differential input, which may be AC coupled. External biasing resistors at the inputs are not required.
Power consumption is typically 160mW using a +3.3V DC power supply.

*SMPTE 259M and SMPTE 344M compliant
*dual coaxial cable driving outputs
*50Ω differential PECL input
*single 3.3V power supply operation
*space-saving 8-lead SOIC
*operating temperature range: 0°C to 70°C
*pin compatible with GS1528 HD-LINX™ II multirate SDI dual slew-rate cable driver
*Pb-free and Green

*SMPTE 259M Coaxial Cable Serial Digital Interfaces

GS9068-CKA, GS9068-CTA, GS9068-CKAE3, GS9068-CTAE3
TAG cable, Driver, SD, SDI

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The GS9090B is a 270Mb/s reclocking deserializer with an internal FIFO.
It provides a complete receive solution for SD-SDI and DVB-ASI applications.
In addition to reclocking and deserializing the input data stream, the GS9090B performs NRZI-to-NRZ decoding, descrambling as per SMPTE 259M-C, and word alignment when operating in SMPTE mode.
When operating in DVB-ASI mode, the device will word align the data to K28.5 sync characters and 8b/10b decode the received stream.
The internal reclocker features a very wide input jitter tolerance, and is fully compatible with both SMPTE and DVB-ASI input streams.
The GS9090B includes a range of data processing functions such as EDH support (error detection and handling), and automatic standards detection.
The device can also detect and extract SMPTE 352M payload identifier packets and independently identify the received video standard.
 This information is read from internal registers via the host interface port.
The GS9090B also incorporates a video line-based FIFO.
This FIFO may be used in four user-selectable modes to carry out tasks such as data alignment / delay, clock phase interchange, MPEG packet extraction and clock rate interchange, and ancillary data packet extraction.
Parallel data outputs are provided in 10-bit multiplexed format, with the associated parallel clock output signal operating at 27MHz.
The device may also be used in a low-latency data pass through mode where only descrambling and word alignment will be performed in SMPTE mode.

Key Features
* SMPTE 259M-C compliant descrambling and NRZI to NRZ decoding (with bypass)
* DVB-ASI sync word detection and 8b/10b decoding
* Integrated line-based FIFO for data alignment/delay, clock phase interchange, DVB-ASI
data packet extraction and clock rate interchange, and ancillary data packet extraction
* Integrated VCO and reclocker
* Automatic or manual selection between SMPTE video and DVB-ASI data
* User selectable additional processing features including:
* TRS, ANC data checksum, and EDH CRC error detection and correction
* programmable ANC data detection
* illegal code remapping
* Internal flywheel for noise immune H, V, F extraction
* Automatic standards detection and indication
* Enhanced Gennum Serial Peripheral Interface (GSPI)
* JTAG test interface
* Polarity insensitive for DVB-ASI and SMPTE signals
* +1.8V core power supply with optional +1.8V or +3.3V I/O power supply
* Small footprint (8mm x 8mm)
* Low power operation (typically 145mW)
* Pb-free

* SMPTE 259M-C Serial Digital Interfaces
* DVB-ASI Serial Digital Interfaces

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