• Synchronizes to standard telecom or Ethernet backplane clocks and provides jitter filtered output clocks for SONET/SDH, PDH and Ethernet network interface cards
• Supports the requirements of ITU-T G.8262 for synchronous Ethernet Equipment slave Clocks (EEC option 1 and 2)
• Two independent DPLLs provides timing for the transmit path (backplane to line rate) and the receive path (recovered line rate to backplane)
• Synchronizes to telecom reference clocks (2 kHz, N*8 kHz up to 77.76 MHz, 155.52 MHz) or to Ethernet reference clocks (25 MHz, 50 MHz, 62.5 MHz, 125 MHz)
• Selectable loop bandwidth of 14 Hz, 28 Hz, 890 Hz, or 0.1 Hz
• Supports automatic hitless reference switching and short term holdover during loss of reference inputs
• Generates standard SONET/SDH clock rates (e.g., 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 MHz, 622.08 MHz) or Ethernet clock rates (e.g. 25 MHz, 50 MHz, 125 MHz, 156.25 MHz, 312.5 MHz) for synchronizing Ethernet PHYs
• Programmable output synthesizers (P0, P1) generate telecom clock frequencies from any
multiple of 8 kHz up to 100 MHz (e.g., T1/E1, DS3/E3)
• Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency
• Configurable input to output delay and output to output phase alignment
• Configurable through a serial interface (SPI or I2C)
• DPLLs can be configured to provide synchronous or asynchronous clock outputs

• ITU-T G.8262 Line Cards which support 1GbE and 10GbE interfaces
• SONET line cards up to OC-192
• SDH line cards up to STM-64


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 The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment.
The S3029 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock.
The chip outputs a differential PECL bit clock and retimed data.
Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO).
The phase detector compares the phase relationship between the VCO output and the serial data input.
A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage.
A block diagram is shown in Figure 2.
There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input.

* Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation
* Five on-chip high frequency PLLs with internal loop filters for clock recovery
* Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data
* Clock Multiplier PLL for transmit clock generation
* 19.44 or 51.84 MHz reference frequency
* Lock detect—monitors run length and frequency
* Low-jitter differential interface
* 3.3V supply
* Available in a 64-pin TQFP package
* Compatible with IgT WAC-413 ATM Quad- UNI processor


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