General Description
The IMP5115 SCSI terminator is part of IMP's family of high-performance, adaptive, non-linear mode SCSI products, which are designed to deliver true UltraSCSI performance in SCSI applications. The low voltage BiCMOS architecture employed in its design offers performance superior to older linear passive and active techniques. IMP's SCSI termination architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible — typically 35MHz, which is 100 times faster than the older linear regulator/terminator approach used by other manufacturers. Products using this older linear
regulator approach have bandwidths which are dominated by the output capacitor and which are limited to 500KHz (see further discussion in the Functional Description section). This new architecture also eliminates the output compensation capacitor required in earlier terminator designs. Each is approved for use with SCSI-1, -2, -3, UltraSCSI and beyond — providing the highest performance alternative available today.
Another key improvement offered by the IMP5115 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as the use of improper cable lengths and impedances. Frequently, this situation not controlled by the peripheral or host designer and, when problems occur, they are the first to be made aware of the problem. The IMP5115 architecture is much more tolerant of marginal system integrations.
Recognizing the needs of portable and configurable peripherals, the IMP5115 has a TTL compatible sleep/disable mode. Quiescent current typically 375μA in this mode, while the output capacitance is also less than 3pF. The obvious advantage of extended battery life for
portable systems is inherent in the product's sleep-mode feature. Additionally, the disable function permits factory-floor or productionline configurability, reducing inventory and product-line diversity costs. Field configurability can also be accomplished without physically removing components which, often times results in field returns due to mishandling.
Reduced component count is also inherent in the IMP5115 architecture. Traditional termination techniques require large stabilization and transient protection capacitors of up to 20μF in value and size. The IMP5115 architecture does not require these components, allowing all the cost savings associated with inventory, board space, assembly, reliability, and component costs.

Key Features
*Ultra-Fast response for Fast-20 SCSI applications
*35MHz channel bandwidth
*3.3V operation
*Less than 3pF output capacitance
*375μA Sleep-mode current
*Thermally self limiting
*No external compensation capacitors
*Implements 8-bit or 16-bit (wide) applications
*Compatible with active negation drivers (60mA/channel)
*Compatible with passive and Active terminations
*Approved for use with SCSI 1, 2, 3 and UltraSCSI
*Hot swap compatible
*Pin-for-pin compatible with DS21S07A/2105

IMP5115CD, IMP5115CDT, IMP5115CDW, IMP5115CDWT, IMP5115CPWP, IMP5115CPWPT

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General Description
The IMP2119 is a multimode SCSI terminator that conforms to the SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10 standards committee for low voltage differential (LVD) termination. Multimode compatibility permits the use of legacy devices on the bus without hardware alterations. Automatic mode selection is achieved through voltage detection on the diffsense line.
The IMP2119 delivers the ultimate in SCSI bus performance while saving component cost and board area. Elimination of the external capacitors also mitigates the need for a lengthy capacitor selection process. The individual high bandwidth drivers also maximize channel separation and reduce channel to channel noise and cross talk. The high bandwidth architecture insures ULTRA3 performance.
When the IMP2119 is enabled, the differential sense (DIFFSENSE) pin supplies a voltage between 1.2V and 1.4V. In application, this pin is tied to the DIFFSENSE input of the corresponding LVD transceivers. This action enables the LVD transceiver function. DIFFSENSE is capable of supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places the IMP2119 in a high impedance state indicating the presence of an HVD device. Tying the pin LOW places the part in a single-ended mode while also signaling the multimode transceiver to operate in a singleended mode.
Recognizing the needs of portable and configurable peripherals, the IMP2119 have a TTL compatible sleep/disable mode. During this sleep/disable mode, power dissipation is reduced to a meager 15μA while also placing all outputs in a high impedance state. Also during sleep/disable mode, the DIFFSENSE function is disabled and is placed in a high impedance state.
Another key feature of the IMP2119 is the master/slave function. Driving this pin HIGH or floating the pin enables the 1.3V DIFFSENSE reference. Driving the pin LOW disables the on board DIFFSENSE reference and enables use of an external master reference device.

Key Features
*Auto-selectable LVD or single-ended termination
*3.0pF maximum disabled output capacitance
*Fast response, no external capacitors required
*Compatible with active negation drivers
*15μA supply current in disconnect mode
*Logic command disconnects all termination lines
*DIFFSENSE line driver
*Ground driver integrated for single-ended operation
*Current limit and thermal protection
*Hot-swap compatible (single-ended)
*Compatible with SCSI, SPI-2, SPI-3, SPI-4 ULTRA160 and ULTRA320
*Pin compatible with DS2119

IMP2119CPW

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DESCRIPTION
 The 9-channel IMP5218 SCSI terminator is part of IMP's family of highperformance SCSI terminators that deliver true UltraSCSI performance.
The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators.
The IMP5218 has two disconnect pins for SCSI Plug and Play (PnP) applications.
IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator terminator approach.
The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required.
The IMP architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs. Reduced component count is inherent with the IMP5218.
The IMP5218 architecture tolerates marginal system designs.
A key improvement offered by the IMP5218 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable lengths and impedance.
Frequently, this situation is not controlled by the peripheral or host designer.
For portable and configurable peripherals, the IMP5218 can be placed in a sleep mode with two disconnect signals.
When disabled, the quiescent current is typically 375μA, and the outputs are in a high impedance state.

Key Features
* SCSI plug and play
- Dual disconnect pins
- Logic LOW disconnects lines
* Hot swap compatible
* Ultra-Fast response for Fast-20 SCSI applications
* 35MHz channel bandwidth
* 3.5V operation
* Less than 3pF output capacitance
* 375μA disable-mode current
* Thermally self limiting
* No external compensation capacitors
* Implements 8-bit or 16-bit (wide) applications
* Compatible with active negation drivers (60mA/channel)
* Compatible with passive and active terminations
* Approved for use with SCSI 1, 2, 3 and UltraSCSI

IMP5218CDW
IMP5218CDWT
IMP5218CPW
IMP5218CPWT

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FEATURES
• Fully compliant with SCSI and SCSI-2 standards
• Backward compatible to the DS2107S
• Provides active termination for 9 signal lines
• Laser-trimmed 110 ohm termination resistors have 1% tolerance
• Low dropout voltage
• Power-down mode isolates termination resistors from the bus
• Handles actively negated SCSI signals
• Onboard thermal shutdown circuitry
• 16-pin plastic SOIC (DS2107AS) and 20-pin plastic thin SSOP (DS2107AE)

DESCRIPTION
The SCSI-2 standard recommends the use of active terminations at both ends of every cable segment in a SCSI system with single-ended drivers and receivers.
The DS2107A SCSI Terminator, which is fully compliant with the standard, enables the designer to gain the benefits of active termination: greater immunity to voltage drops on the TERMPWR (TERMination PoWeR) line, enhanced high-level noise immunity, intrinsic TERMPWR decoupling, and very low quiescent current consumption. The DS2107A integrates a regulator and nine precise switched 110 ohm termination resistors into a monolithic IC.

FUNCTIONAL DESCRIPTION
The DS2107A consists of a bandgap reference, buffer amplifier, and nine termination resistors (Figure 1). The bandgap reference circuit produces a precise 2.55V level which is fed to a buffer amplifier. The buffer produces a 2.85V level and is capable of sourcing at least 24 mA into each of the termination resistors when the signal line is low (active). When the driver for a given signal line turns off, the terminator will pull the signal line to 2.85V (quiescent state). To handle actively negated SCSI signals, the buffer can sink 200 mA. When all lines settle in the quiescent state, the regulator will consume about 5 mA. When the DS2107A is put into powerdown mode by bringing PD low, the power-down circuitry will turn off the transistors on each signal line. This will isolate the DS2107A from the signal lines and effectively remove it from the circuit. The power-down pin (PD) has an internal 50K ohm pull-up resistor. To place the DS2107A into an active state, the PD pin should be left open circuited.
To ensure proper operation, both the TERMPWR1 and TERMPWR2 pins must be connected to the SCSI bus TERMPWR line and both the VREF1 and VREF2 pins must be tied together externally. Each DS2107A requires parallel 0.1 mF and 4. 7 mF capacitors connected between the VREF pins and ground. Figure 2 details a typical SCSI bus configuration. In an 8-bit wide SCSI bus arrangement (“A” Cable), two DS2107A’s would be needed at each end of the SCSI cable in order to terminate the 18 active signal lines. In a 16-bit wide SCSI bus arrangement (“P” Cable), three DS2107A’s would be needed at each end of the SCSI cable in order to terminate the 27 active signal lines.


DS2107AS
DS2107AE

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DISTINCTIVE CHARACTERISTICS
* Pin/function compatible with Emulex FAS216/236
* AMD’s Patented programmable GLITCH EATERTM Circuitry on REQ and ACK inputs
* 10 Mbytes/s synchronous Fast SCSI transfer rate
* 20 Mbytes/s DMA transfer rate
* 16-Bit DMA interface plus 2 bits of parity
* Flexible three bus architecture
* Single-ended SCSI bus supported by Am53CF94
* Differential SCSI bus supported by Am53CF96
* Selection of multiplexed or non-multiplexed address and data bus
* High current drivers (48 mA) for direct connection to the single-ended SCSI bus
* Supports Disconnect and Reselect commands
* Supports burst mode DMA operation with a threshold of eight
* Supports 3-byte tagged-queueing as per the SCSI-2 specification
* Supports group 2 and 5 command recognition as per the SCSI-2 specification
* Advanced CMOS process for lower power consumption
* AMD’s exclusive programmable power-down feature
* 24-Bit extended transfer counter allows for data block transfer of up to 16 Mbytes
* Independently programmable 3-byte message and group 2 identification
* Additional check for ID message during bus-initiated Select with ATN
* Reselection has QTAG features of ATN3
* Access FIFO Command
* Delayed enable signal for differential drivers avoid contention on SCSI differential lines
* Programmable Active Negation on REQ, ACK and Data lines
* Register programmable control of assertion/ deassertion delay for REQ and ACK lines
* Part-unique ID code
* Am53CF94 available in 84-pin PLCC package
* Am53CF96 available in 100-pin PQFP package
* Am53CF94 available in 3.3 V version
* Supports clock operating frequencies from 10 MHz–40 MHz
* Supports Scatter-Gather or Back-to-Back synchronous data transfers

GENERAL DESCRIPTION
 The Enhanced SCSI-2 Controller (ESC) was designed to support Fast SCSI-2 transfer rates of up to 10 Mbytes/s in synchronous mode and up to 7 Mbytes/s in the asynchronous mode. The ESC is downward compatible with the Am53C94/96, combining its functionality with features such as Fast SCSI, programmable Active Negation, a 24-bit transfer counter, and a part-unique ID code containing manufacturer and serial # information.
 AMD’s proprietary features such as power-down mode for SCSI transceivers, programmable GLITCH EATER, and extended Target command set are also included for improved product performance.

 The Enhanced SCSI-2 Controller (ESC) has a flexible three bus architecture. The ESC has a 16-bit DMA interface, an 8-bit host data interface and an 8-bit SCSI data interface. The ESC is designed to minimize host intervention by implementing common SCSI sequences in hardware. An on-chip state machine reduces protocol overheads by performing the required sequences in response to a single command from the host. Selection,  reselection, information transfer and disconnection commands are directly supported.

 The 16-byte-internal FIFO further assists in minimizing host involvement. The FIFO provides a temporary storage for all command, data, status and message bytes as they are transferred between the 16-bit host data bus and the 8-bit SCSI data bus. During DMA operations the FIFO acts as a buffer to allow greater latency in the DMA channel. This permits the DMA channel to be suspended for higher priority operations such as DRAM refresh or reception of an ISDN packet.

 Parity on the DMA bus is optional. Parity can either be generated and checked or it can be simply passed through.

 The Target command set for the Am53CF94/96 includes an additional command, the Access FIFO command, to allow the host or DMA controller to remove remaining FIFO data following the host’s issuance of a Target abort DMA command or following an abort due to parity error. This command facilitates data recovery and thereby minimizes the need to re-transmit data. AMD’s exclusive power-down feature can be enabled to help reduce power consumption during the chip’s sleep mode. The receivers on the SCSI bus may be turned off to eliminate current that may flow because termination power (~3 V) is close to the trip point of the input buffers.

 The patented GLITCH EATER Circuitry in the Enhanced SCSI-2 Controller can be programmed to filter glitches with widths up to 35 ns. It is designed to dramatically increase system reliability by detecting and removing glitches that may cause system failure. The GLITCH EATER Circuitry is implemented on the ACK and REQ lines since they are most susceptible to electrical anomalies such as reflections and voltage spikes. Such signal inconsistencies can trigger false REQ/ACK handshaking, false data transfers, addition of random data, and double clocking. AMD’s GLITCH EATER Circuitry therefore maintains system performance and improves reliability. The following diagram illustrates this circuit’s operation.

The Am53CF94 is also available in a 3.3 V version.

AM53CF96 AM53CF96JC AM53CF96KC AM53CF96JC/W AM53CF96KC/W AM53CF94JC
AM53CF94KC AM53CF94JC/W AM53CF94KC/W


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