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  1. 2008/09/18 AZ10E142-ECL/PECL 9-bit Shift Register
The AZ10/100E142 is a 9-bit shift register, designed with byte-parity applications in mind. The E142 performs serial/parallel in and serial/parallel out, shifting in one direction. The nine inputs D0-D8 accept parallel input data, while S-IN accepts serial input data. The Qn outputs do not need to be terminated for the shift operation to function.
To minimize noise and power, any Q output not used should be left unterminated.
The SEL (Select) input pin is used to switch between the two modes of operation – SHIFT and LOAD. The shift direction is from bit 0 to bit 8. Input data is accepted by the registers a set-up time before the positive going edge of CLK1 or CLK2; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.

*700 MHz Minimum Shift Frequency
*9-Bit for Byte-Parity Application
*Asynchronous Master Reset
*Dual Clocks
*Operating Range of 4.2V to 5.46V
*75kΩ Internal Input Pulldown Resistors
*Direct Replacement for ON Semi MC10E142 & MC100E142

AZ100E142, AZ10E142FN, AZ100E142FN

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