Description
The EBE21RD4ABHA is a 256M words × 72 bits, 2 ranks DDR2 SDRAM Module, mounting 36 pieces of 512M bits DDR2 SDRAM with sFBGA stacking technology. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 4bits prefetchpipelined architecture. Data strobe (DQS and /DQS) both for read and write are available for high speed and reliable data bus design. By setting extended mode register, the on-chip Delay Locked Loop (DLL) can be set enable or disable. This module provides high density mounting without utilizing surface mount technology. Decoupling capacitors are mounted beside each SDRAM on the module board.

Features
*240-pin socket type dual in line memory module (DIMM)
-PCB height: 30.0mm
-Lead pitch: 1.0mm
-Lead-free
*1.8V power supply
*Data rate: 533Mbps/400Mbps (max.)
*1.8 V (SSTL_18 compatible) I/O
*Double-data-rate architecture: two data transfers per clock cycle
*Bi-directional, data strobe (DQS and /DQS) is transmitted /received with data, to be used in
capturing data at the receiver
*DQS is edge aligned with data for READs; center aligned with data for WRITEs
*Differential clock inputs (CK and /CK)
*DLL aligns DQ and DQS transitions with CK transitions
*Commands entered on each positive CK edge; data referenced to both edges of DQS
*Four internal banks for concurrent operation (Components)
*Burst length: 4, 8
*/CAS latency (CL): 3, 4, 5
*Auto precharge option for each burst access
*Auto refresh and self refresh modes
*7.8μs average periodic refresh interval
*Posted CAS by programmable additive latency for better command and data bus efficiency
*Off-Chip-Driver Impedance Adjustment and On-Die-Termination for better signal quality
*/DQS can be disabled for single-ended Data Strobe operation
*1 piece of PLL clock driver, 4 piece of register driver and 1 piece of serial EEPROM (2k bits EEPROM) for Presence Detect (PD)

EBE21RD4ABHA-5C-E, EBE21RD4ABHA-4A-E

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DESCRIPTION
This registered bus exchanger is built using advanced dual metal CMOS technology. The ALVCH16270 is used in applications in which data must be transferred from a narrow high-speed bus to a wide lower-frequency bus. This device provides synchronous data exchange between the two ports. Data is stored in the internal registers on the low-to-high transition of the clock CLK) input when the appropriate clock-enable (CLKEN) inputs are low. The select (SEL) line selects 1B or 2B data for the A outputs. For data transfer in the A-to-B direction, a two-stage pipeline is provided in the A-to-1B path, with a single storage register in the A-to-2B path. Proper control of the CLKENA input allows two sequential 12-bit words to be presented synchronously as a 24-bit word on the B-port. Data flow is controlled by the active-low output enables (OEA and OEB). The control terminals are registered to synchronize the bus-direction
changes with CLK.
The ALVCH16270 has been designed with a ±24mA output driver. This driver is capable of driving a moderate to heavy load while maintaining speed performance.
The ALVCH16270 has “bus-hold” which retains the inputs’ last state whenever the input goes to a high impedance. This prevents floating inputs and eliminates the need for pull-up/down resistors.

FEATURES
*0.5 MICRON CMOS Technology
*Typical tSK(o) (Output Skew) < 250ps
*ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
*VCC = 3.3V ± 0.3V, Normal Range
*VCC = 2.7V to 3.6V, Extended Range
*VCC = 2.5V ± 0.2V
*CMOS power levels (0.4μ W typ. static)
*Rail-to-Rail output swing for increased noise margin
*Available in SSOP, TSSOP, and TVSOP packages

DRIVE FEATURES
*High Output Drivers: ±24mA
*Suitable for heavy loads

APPLICATIONS
*3.3V high speed systems
*3.3V and lower voltage computing systems

IDT74ALVCH16270PV, IDT74ALVCH16270PA, IDT74ALVCH16270PF

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Product Description
Pericom Semiconductor’s PI74LCX series of logic circuits are produced in the Company’s advanced 0.6 micron CMOS technology, achieving industry leading speed grades.
The PI74LCX646 and PI74LCX652 are designed with a bus transceiver with 3-state D-type flip-flops and control circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The PI74LCX652 utilizes GAB and GBA signals to control the transceiver functions. The PI74LCX646 uses the enable control (G) and direction pins (DIR) to control the transceiver functions. SAB and SBA control pins are used to select either real-time or stored data transfer. The circuitry used for select control will eliminate the typical decoding glitch that occurs in a multiplexer during the transition between real-time and
stored data. A low input level selects real-time data and a high selects stored data.
The PI74LCX646 and PI74LCX652 can be driven from either 3.3V or 5.0V devices allowing this device to be used as a translator in a mixed 3.3/5.0V system.

Product Features
*Functionally compatible with FCT3, LVT, and 74 series 646 and 652 families of products
*Tri-State outputs
*5V Tolerant inputs and outputs
*2.0V-3.6V VCC supply operation
*Balanced sink and source output drives (24 mA)
*Low ground bounce outputs
*Supports live insertion
*ESD Protection exceeds 2000V, Human Body Model 200V, Machine Model
*Packages available:
– 24-pin 209-mil wide plastic SSOP (H)
– 24-pin 173-mil wide plastic TSSOP (L)
– 24-pin 150-mil wide plastic QSOP (Q)
– 24-pin 300-mil wide plastic SOIC (S)

PI74LCX652

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