DESCRIPTION
The IDT29FCT520A/B/C contains four 8-bit positive edgetriggered registers.
These may be operated as a dual 2-level or as a single 4-level pipeline.
A single 8-bit input is provided and any of the four registers is available at the 8-bit, 3-state
output.
In the IDT29FCT520A/B/C when data is entered into the first level (I = 2 or I = 1), the existing data in the first level is moved to the second level.
Transfer of data to the second level is achieved using the 4-level shift instruction (I = 0).
This transfer also causes the first level to change.

FEATURES
*Equivalent to AMD’s Am29520 bipolar Multilevel Pipeline Register in pinout/function, speed and output drive over full temperature and voltage supply extremes
*Four 8-bit high-speed registers
*Dual two-level or single four-level push-only stack operation
*All registers available at multiplexed output
*Hold, transfer and load instructions
*Provides temporary address or data storage
*IOL = 48mA (commercial), 32mA (military)
*CMOS power levels (1mW typ. static)
*Substantially lower input current levels than AMD’s bipolar (5mA typ.)
*TTL input and output level compatible
*CMOS output level compatible
*Manufactured using advanced CMOS processing
*Available in 300 mil plastic and hermetic DIP, as well as LCC, SOIC and CERPACK
*Product available in Radiation Tolerant and Radiation Enhanced versions
*Military product compliant to MIL-STD-883, Class B

IDT29FCT520B
IDT29FCT520C

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General Description
The MAX16047/MAX16049 EEPROM-configurable system managers monitor, sequence, and track multiple system voltages. The MAX16047 manages up to twelve system voltages simultaneously, and the MAX16049 manages up to eight supply voltages. These devices integrate an analog- to-digital converter (ADC) for monitoring supply voltages, and configurable outputs for sequencing and tracking supplies (during power-up and power-down).
Nonvolatile EEPROM registers are configurable for storing upper and lower voltage limits, setting timing and sequencing requirements, and for storing critical fault data for read back following failures.
An internal 1% accurate 10-bit ADC measures each input and compares the result to one upper, one lower, and one selectable upper or lower limit. A fault signal asserts when a monitored voltage falls outside the set limits. Up to three independent fault output signals are configurable to assert under various fault conditions.
The integrated sequencer/tracker allows precise control over the power-up and power-down order of up to twelve (MAX16047) or up to eight (MAX16049) power supplies.
Four channels (EN_OUT1–EN_OUT4) support closedloop tracking using external series MOSFETs. Six outputs (EN_OUT1–EN_OUT6) are configurable with chargepump outputs to directly drive MOSFETs without closedloop tracking.
The MAX16047/MAX16049 include six programmable general-purpose inputs/outputs (GPIOs). In addition to serving as EEPROM-configurable I/O pins, the GPIOs are also configurable as dedicated fault outputs, as a watchdog input or output (WDI/WDO), or as a manual reset (MR).
The MAX16047/MAX16049 feature two methods of fault management for recording information during critical fault events. The fault logger records a failure in the internal EEPROM and sets a lock bit protecting the stored fault data from accidental erasure.
An I2C/SMBus™-compatible or a JTAG serial interface configures the MAX16047/MAX16049. These devices are offered in a 56-pin 8mm x 8mm TQFN package and are fully specified from -40°C to +85°C.

Features
* Operates from 3V to 14V
* 1% Accurate 10-Bit ADC Monitors 12/8 Inputs
* 12/8 Monitored Inputs with One Overvoltage/ One Undervoltage/One Selectable Limit
* Nonvolatile Fault Event Logger
* Power-Up and Power-Down Sequencing Capability
* 12/8 Outputs for Sequencing/Power-Good Indicators
* Closed-Loop Tracking for Up to Four Channels
* Two Programmable Fault Outputs and One Reset Output
* Six General-Purpose Input/Outputs Configurable as:
Dedicated Fault Output
Watchdog Timer Function
Manual Reset
* I2C/SMBus-Compatible and JTAG Interface
* EEPROM-Configurable Time Delays and Thresholds
* 100 Bytes of Internal User EEPROM
* 56-Pin (8mm x 8mm) TQFN Package
* -40°C to +85°C Operating Temperature Range

MAX16047ETN
MAX16049ETN

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Features
• CMOS for optimum speed/power
• Windowed for reprogrammability
• High speed
-tSA = 45 ns
-tCO = 15 ns
• Low power
-120 mA
• On-chip, edge-triggered output registers
• Programmable synchronous or asynchronous output enable
• EPROM technology, 100% programmable
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
• Slim 300-mil package
• Capable of withstanding >2001V static discharge

Functional Description
The CY7C287 is a high-performance 64K x 8 CMOS PROM.
The CY7C287 is equipped with an output register and an output output enable that can be programmed to be synchronous (ES) or asynchronous (E). It is available in a 28-pin, 300-mil package.
The address set-up time is 45 ns and the time from clock HIGH to output valid is 15 ns.
The CY7C287 is available in a cerDIP package equipped with an erasure window to provide reprogrammability. When exposed to UV light, the PROM is erased and can be reprogrammed.
The memory cells utilize proven EPROM floating- gate technology and byte-wide intelligent programming algorithms.
The CY7C287 offers the advantage of low power, superior performance, and programming yield. The EPROM cell requires only 12.5V for the supervoltage and low current requirements
allow for gang programming. The EPROM cells allow for each memory location to be 100% tested with each cell being programmed, erased, and repeatedly exercised prior to encapsulation.
Each PROM is also tested for AC performance to guarantee that the product will meet DC and AC specification limits after customer programming.
Reading the CY7C287 is accomplished by placing an active LOW signal on E/ES. The contents of the memory location addressed by the address lines (A0 - A15) will become available on the output lines (O0 - O7) on the next rising of CP.

CY7C287-45JC
CY7C287-45PC
CY7C287-45WC

TAG Register

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Features
* Low voltage power supply down to 3V
* 8 constant current output channels
* Adjustable output current through external resistor
* Serial Data IN/Parallel data OUT
* 3.3V micro driver-able
* Output current: 5-100mA
* 30MHz clock frequency
* Available in high thermal efficiency TSSOP exposed pad
* ESD protection 2.5kV HBM, 200V MM

Description
The STP08CP05 is a monolithic, low voltage, low current, power 8-bit shift register designed for
LED panel displays. The STP08CP05 contains a 8-bit serial-in, parallel-out shift register that feeds a 8-bit D-type storage register. In the output stage, eight regulated current sources were designed to provide 5-100mA constant current to drive the LEDs, the output current setup time is 10ns (typ), thus improving the system performance.
The STP08CP05 is backward compatible in functionality and footprint with STP8C/L596.
Through an external resistor, users can adjust the STP08CP05 output current, controlling in this way the light intensity of LEDs, in addition, user can adjust LED’s brightness intensity from 0% to 100% via OE pin.
The STP08CP05 guarantees a 20V output driving capability, allowing users to connect more LEDs in series. The high clock frequency, 30 MHz, also satisfies the system requirement of high volume data transmission. The 3.3V of voltage supply is useful for applications that interface with any micro from 3.3V. Compared with a standard TSSOP package, the TSSOP exposed pad increases heat dissipation capability by a 2.5 factor.

STP08CP05B1R
STP08CP05MTR
STP08CP05TTR
STP08CP05XTTR

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FEATURES
• Common features:
– 0.5 MICRON CMOS Technology
– High-speed, low-power CMOS replacement for ABT functions
– Typical tSK(o) (Output Skew) < 250ps
– Low input and output leakage £1mA (max.)
– ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)
– Packages include 25 mil pitch SSOP, 19.6 mil pitch TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
– Extended commercial range of -40°C to +85°C
– VCC = 5V ±10%
• Features for FCT16374T/AT/CT/ET:
– High drive outputs (-32mA IOH, 64mA IOL)
– Power off disable outputs permit “live insertion”
– Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V, TA = 25°C
• Features for FCT162374T/AT/CT/ET:
– Balanced Output Drivers: ±24mA (commercial), ±16mA (military)
– Reduced system switching noise
– Typical VOLP (Output Ground Bounce) < 0.6V at VCC = 5V,TA = 25°C

DESCRIPTION
The FCT16374T/AT/CT/ET and FCT162374T/AT/CT/ET 16-bit edge-triggered D-type registers are built using advanced dual metal CMOS technology. These high-speed, low-power registers are ideal for use as buffer registers for data synchronization and storage. The Output Enable (xOE) and clock (xCLK) controls are organized to operate each device as two 8-bit registers or one 16-bit register with common clock. Flow-through organization of signal pins simplifies layout. All inputs are designed with hysteresis for improved noise margin.
The FCT16374T/AT/CT/ET are ideally suited for driving high-capacitance loads and low-impedance backplanes. The output buffers are designed with power off disable capability to allow "live insertion" of boards when used as backplane drivers.
The FCT162374T/AT/CT/ET have balanced output drive with current limiting resistors. This offers low ground bounce, minimal undershoot, and controlled output fall times– reducing the need for external series terminating resistors. The FCT162374T/AT/CT/ET are plug-in replacements for the FCT16374T/AT/CT/ET and ABT16374 for on-board bus interface applications.

DT54FCT16374AT
IDT74FCT16374AT
IDT54FCT16374CT
TAG CMOS, Register

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Product Features
· PI74ALVCH16646 is designed for low voltage operation
· VCC = 2.3V to 3.6V
· Hysteresis on all inputs
· Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
· Typical VOHV (Output VOH Undershoot)
< 2.0V at VCC = 3.3V, TA = 25°C
· Bus Hold retains last active bus state during 3-STATE, eliminating the need for external pullup resistors
· Industrial operation at –40°C to +85°C
· Packages available:
 56-pin 240 mil wide plastic TSSOP (A)
 56-pin 300 mil wide plastic SSOP (V)

Product Description
Pericom Semiconductor’s PI74ALVCH series of logic circuits are produced in the Company’s advanced 0.5 micron CMOS technology, achieving industry leading speed.
The PI74ALVCH16646 is a 16-bit bus transceiver and register designed for 2.3V to 3.6V VCC operation. It can be used as two 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate Clock (CLKAB or CLKBA) input. Four fundamental bus-management functions can be performed.
Output Enable (OE) and Direction Control (DIR) inputs are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The Select Control (SAB and SBA) inputs can multiplex stored and real-time (transparent mode) data. Circuitry used for Select Control eliminates the typical decoding glitch that occurs in a multiplexer during the transition between stored and real-time
data. DIR determines which bus receives data when OE is LOW. In the isolation mode (OE HIGH), A data may be stored in one register and/or B data may be stored in the other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, can be driven at a time.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

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Features
• PI74SSTU32864A is designed for low-voltage operation,VDD = 1.8V
• Supports Low Power Standby Operation
• Enhanced Signal Integrity for 1 and 2 Rank Modules
• All Inputs are SSTL_18 Compatible, except RST, C0, C1, which are LVCMOS.
• Output drivers are optimized to drive DDR2 DIMM loads
• Designed for DDR2 Memory
• Packaging (Pb-free & Green available):
-96 Ball LFBGA (NB)

Description
Pericom Semiconductor’s PI74SSTU32864A logic circuit is produced using advanced CMOS technology. This 25-Bit 1:1 or 14-Bit 1:2 configurable registered buffer is designed for 1.7V to 1.9V VDD operation.
All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8V LVCMOS drivers that have been optimized to drive the DDR2 DIMM load.
The SSTU32864A operates from a differential clock (CK and CK). Data is registered at the crossing of CK going high, and CK going low.
The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration for 25-Bit 1:1 (when LOW) to 14-Bit 1:2 (when HIGH).
The device supports low-power standby operation. When the reset input (RST) is low, the differential input receivers are disabled and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition , when RST is low, all registers are reset, and all outputs are forced low. The LVCMOS RST and Cn inputs must always be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RST must be held in the low state during power up.
In the DDR-II RDIMM application, RST is specified to be completely asynchronous with respect to CK and CK. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers.
As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RST until the input receivers are fully enabled, the design of the SSTU32864A must ensure that the outputs remain low, thus ensuring no glitches on the output.
The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn outputs will function normally. The RST input has priority over the DCS and CSR control will force the outputs low. If the DCS control functionality is not desired, then the CSR input can be hardwired to ground, in which case, the set-up time requirement for DCS would be the same as for the other D data inputs.


PI74SSTU32864ANB
PI74SSTU32864ANBE

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* Function, Pinout, and Drive Compatible With FCT and F Logic
* Reduced VOH (Typically = 3.3 V) Versions of Equivalent FCT Functions
* Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
* Ioff Supports Partial-Power-Down Mode Operation
* Matched Rise and Fall Times
* Fully Compatible With TTL Input and Output Logic Levels
* ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
* Edge-Triggered D-Type Inputs
* 250-MHz Typical Switching Rate
* CY54FCT374T
– 32-mA Output Sink Current
– 12-mA Output Source Current
* CY74FCT374T
– 64-mA Output Sink Current
– 32-mA Output Source Current
* 3-State Outputs

description
The ’FCT374T devices are high-speed, low-power, octal D-type flip-flops, featuring separate D-type inputs for each flip-flop. These devices have 3-state outputs for bus-oriented applications. A buffered clock (CP) and output-enable (OE) inputs are common to all flip-flops. The eight flip-flops in the ’FCT374T store the state of their individual D inputs that meet the setup-time and hold-time requirements on the low-to-high CP transition.
When OE is low, the contents of the eight flip-flops are available at the outputs. When OE is high, the outputs are in the high-impedance state. The state of OE does not affect the state of the flip-flops.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

CY74FCT374CTQCT
CY74FCT374CTSOC
CY74FCT374CTSOCT
CY74FCT374ATPC
CY74FCT374ATQCT
CY74FCT374ATSOC
CY74FCT374ATSOCT
CY74FCT374TQCT
CY74FCT374TSOC
CY74FCT374TSOCT
CY54FCT374CTDMB
CY54FCT374CTLMB
CY54FCT374ATDMB
CY54FCT374ATLMB
CY54FCT374TDMB
CY54FCT374TLMB

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Description
The MC74HC595A consists of an 8–bit shift register and an 8–bit D–type latch with three–state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8–bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register.
The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.

• Output Drive Capability: 15 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 328 FETs or 82 Equivalent Gates
• Improvements over HC595
  - Improved Propagation Delays
  - 50% Lower Quiescent Power
  - Improved Input Noise and Latchup Immunity

MC74HC595AN, MC74HC595AD, MC74HC595ADR2, MC74HC595ADT, MC74HC595ADTR2

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