San Jose, California − December 4, 2007 − Fairchild Semiconductor’s (NYSE: FCS) FDMF8704 and FDMF8704V optimize efficiency across high, medium and light loads in ultra-dense servers, blade servers, advanced gaming systems, small form factor desktops, media center PCs, graphic cards, networking and telecom equipment, and other DC-DC applications. Most computing applications do not run at 100 percent load all the time and delivering the right performance at the right current levels reduces power losses for these applications. Average power losses across the full operating range are reduced by 14 percent compared to conventional discrete solutions by using Fairchild’s driver plus FET multi-chip modules, and these systems can more easily meet the demand for higher efficiency mandated by energy regulatory programs such as Energy Star.

The FDMF8704 and FDMF8704V are FET plus driver power stage solutions that integrate one driver IC, three power MOSFETs and one Schottky diode into an 8mm x 8mm MLP package, conserving valuable PCB real estate. The FDMF8704 is capable of operating at 1MHz eliminating passive components to further reduce board space and lower BOM costs. Compared to conventional discrete solutions, Fairchild’s DrMOS saves more than 72 percent of valuable board space.

The FDMF8704 and the FDMF8704V are both based on the Intel® specification for DrMOS. The FDMF8704 maximizes efficiency through a low-impedance driver IC and Fairchild’s latest PowerTrench® MOSFET technology. The FDMF8704 is ideal for applications such as servers that need to maximize efficiency. The FDMF8704V features a convenient built-in voltage regulator block for applications with only a 12V rail available.

“Fairchild is an industry leader in DrMOS solutions. Our extensive DrMOS portfolio provides designers with the flexibility to choose the right performance, at the right price, for the right application,” says Roberto Guerrero, worldwide segment manager for Desktop, Server and Gaming products.

The FDMF8704 and FDMF8704V utilize lead-free (Pb-free) terminals and have been characterized for moisture sensitivity in accordance with the Pb-free reflow requirements of the joint IPC/JEDEC standard J-STD-020. All of Fairchild's products are designed to meet the requirements of the European Union's Directive on the restriction of the use of certain substances (RoHS).

Price (each, 1000 pcs): FDMF8704 US $3.00
FDMF8704V US $3.00

Availability: Samples available now

Delivery: 12 weeks ARO

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General Description
The WPCN381U, a member of the Winbond LPC SuperI/O family, is targeted for legacy-reduced ultra-light portable applications.
The WPCN381U is PC2001 and ACPI compliant, and features a Fast Infrared port (FIR, IrDA 1.1 compliant), two Serial Ports and General-Purpose Input/Output (GPIO) support for a total of 11 ports.
The WPCN381U is a “no-frills” solution for the new generation of notebook systems, providing just the essential functions.

Outstanding Features
* Pin and software compatible with the Winbond 87381
* Fast Infrared Port (FIR)
* Two Serial Ports
* LPC bus interface, based on Intel’s LPC Interface Specification Revision 1.1, August 2002 (supports CLKRUN and LPCPD signals)
* PC2001 and ACPI Revision 3.0 compliant
* 11 GPIO ports, including 6 with IRQ assertion capability
* Two testability modes (XOR Tree and TRI-STATE® device pins).
* 5V tolerant and back-drive protected pins (except LPC bus pins)
* 48-pin LQFP package

* Fast Infrared Port (FIR)
- Software compatible with the 16550A and the 16450
- Shadow register support for write-only bit monitoring
- FIR IrDA 1.1 compliant
- ASK-IR option of SHARP-IR
- DASK-IR option of SHARP-IR
- Consumer Remote Control supports RC-5, RC-6, NEC, RCA and RECS 80
- DMA support: one or two channels
* Two Serial Ports (SP1 and SP2)
- SP2 can be used only when FIR is not needed
- Software compatible with the 16550A and the 16450
- Shadow register support for write-only bit monitoring
- UART data rates up to 1.5 Mbaud
* 11 General-Purpose I/O (GPIO) Ports
- Supports IRQ assertion
- Programmable drive type for each output pin (opendrain, push-pull or output disable)
- Programmable option for internal pull-up resistor on each input pin
- Output lock option
- Input debounce mechanism
* LPC System Interface
- 8-bit I/O cycles
- LPCPD and CLKRUN support
- Implements PCI mobile design guide recommendation (PCI Mobile Design Guide 1.1, Dec. 18, 1998)
* PC2001 and ACPI 3.0 Compliant
- PnP Configuration Register structure
- Flexible resource allocation for all logical devices
+ Relocatable base address
+ 15 IRQ routing options
+ Optional 8-bit DMA channels (where applicable) selected from four possible DMA channels
* Clock Sources
- 14.318 MHz or 48 MHz clock input
- LPC clock, 0 or 30 MHz to 33 MHz
* Strap Configuration
- Base Address (BADDR) strap to determine the base address of the Index-Data register pair
- Strap Inputs to select testability mode
* Power Supply
- 3.3V supply operation
- All pins are 5V tolerant, except LPC bus pins
- All pins are back-drive protected, except LPC bus pins
* Testability
- XOR Tree
- TRI-STATE device pins

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