The EM44AM1684LBA is a high speed Double Date Rate 2 (DDR2) Synchronous DRAM fabricated with ultra high performance CMOS process containing 268,435,456 bits which organized as 4Mbits x 4 banks by 16 bits.
This synchronous device achieves high speed double-data-rate transfer rates of up to 667 Mb/sec/pin (DDR2-667) for general applications.
The chip is designed to comply with the following key DDR2 SDRAM features: (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) Off-Chip Driver (OCD) impedance adjustment and On Die Termination (4) normal and weak strength data output driver.
All of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and /CK falling). All I/Os are synchronized with a pair of bidirectional strobes (DQS and /DQS) in a source synchronous fashion. The address bus is used to convey row, column and bank address information in a /RAS and /CAS multiplexing style.
The 512Mb DDR2 device operates with a single power supply: 1.8V ± 0.1V VDD and VDDQ.
Available package: TFBGA-84Ball (12.5mmx10mm, 0.8mm x 0.8mm ball pitch).

*JEDEC Standard VDD/VDDQ=1.8V ± 0.1V.
*All inputs and outputs are compatible with SSTL_18 interface.
*Fully differential clock inputs (CK,/CK) operation.
*4 Banks
*Posted CAS
*Burst Length: 4 and 8.
*Programmable CAS Latency (CL): 3, 4 and 5.
*Programmable Additive Latency (AL): 0, 1, 2, 3 and 4.
*Write Latency (WL) =Read Latency (RL) -1.
*Read Latency (RL) = Programmable Additive Latency (AL) + CAS Latency (CL)
*Bi-directional Differential Data Strobe (DQS).
*Data inputs on DQS centers when write.
*Data outputs on DQS, /DQS edges when read.
*On chip DLL align DQ, DQS and /DQS transition with CK transition.
*DM mask write data-in at the both rising and falling edges of the data strobe.
*Sequential & Interleaved Burst type available.
*Off-Chip Driver (OCD) Impedance Adjustment
*On Die Termination (ODT)
*Auto Refresh and Self Refresh
*8,192 Refresh Cycles / 64ms
*Average Refresh Period 7.8us at lower than Tcase 85°C, 3.9us at 85°C < Tcase ≦ 95°C
*RoHS Compliance
*Partial Array Self-Refresh (PASR)
*High Temperature Self-Refresh rate enable

EM44AM1684LBA-5F, EM44AM1684LBA-37F, EM44AM1684LBA-3F

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 The GS1582 is the next generation multi-standard serializer with an integrated cable driver.
The device provides robust parallel to serial conversion, generating a SMPTE 292M/259M-C compliant serial digital output signal.
The integrated cable driver features an output disable (high impedance) mode and an adjustable signal swing.
Data input is accepted in 20-bit parallel format or 10-bit parallel format. An associated parallel clock input must be provided at the appropriate operating frequency; 74.25/74.1758/13.5MHz (20-bit mode) or 148.5/148.352/27MHz (10-bit mode).
The GS1582 features an internal PLL which, if desired, can be configured for a loop bandwidth below 100kHz.
When used in conjunction with the GO1555 Voltage Controlled Oscillator, the GS1582 can tolerate well in excess of 300ps jitter on the input PCLK and still provide output jitter within SMPTE specifications.
In addition to serializing the input, the GS1582 performs NRZ-to-NRZI encoding and scrambling as per SMPTE 292M/259M-C when operating in SMPTE mode.
When operating in DVB-ASI mode, the device will insert K28.5 sync characters and 8b/10b encode the data prior to serialization.
The device also provides a range of other data processing functions.
All processing features are optional and may be enabled/disabled via external control pin(s) and/or host interface programming.
The GS1582 can embed up to 8 channels of audio into the video data stream in accordance with SMPTE 299M and SMPTE 272M.
The audio input signal formats supported by the device include AES/EBU and I2S serial digital formats with a 16, 20 or 24 bit sample size and a 48 kHz sample rate.
Additional audio processing features include individual channel enable, channel swap, group swap, ECC generation and audio channel status insertion.
Typical power consumption, including the GO1555 VCO, is 500mW.
The standby feature allows the power to be reduced to 125mW.
Power may be reduced to less than 10mW by also removing the power to the cable driver and eliminating transitions at the parallel data and clock inputs.
The GS1582 is Pb-free and RoHS compliant.

Key Features
* HD-SDI, SD-SDI, DVB-ASI transmitter with audio embedding
* Integrated SMPTE 292M and 259M-C compliant cable driver
* Integrated ClockCleaner™
* User selectable video processing features, including:
* Generic ancillary data insertion
* Support for HVF or EIA/CEA-861 timing input
* Automatic standard detection and indication
* Enhanced SMPTE 352M payload identifier generation and insertion
* TRS, CRC, ANC data checksum, and line number calculation and insertion
* EDH packet generation and insertion
* Illegal code remapping
* SMPTE 292M and SMPTE 259M-C compliant scrambling and NRZ → NRZI encoding
* Blanking of input HANC and VANC space
* User selectable audio processing features, including:
* SMPTE 299M and SMPTE 272M-A/C compliant audio embedding
* Support for up to 8 channels
* Support for audio group replacement
* JTAG test interface
* 1.8V core and 3.3V charge pump power supply
* 1.8V and 3.3V digital I/O support
* Low power standby mode
* Operating temperature range: -20oC to +85oC
* Pb-free, RoHS compliant, 11mm x 11mm 100-ball BGA package

* SMPTE 292M and SMPTE 259M-C Serial Digital Interfaces
* DVB-ASI Serial Digital Interfaces


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• 2.5V + 5% power supply for device operation
• 2.5V + 5% power supply for I/O interface
• SSTL_2 compatible inputs/outputs
• 4 banks operation
• MRS cycle with address key programs
-. Read latency 3,4,5 (clock)
-. Burst length (2, 4, 8 and Full page)
-. Burst type (sequential & interleave)
• Full page burst length for sequential burst type only
• Start address of the full page burst should be even
• All inputs except data & DM are sampled at the positive going edge of the system clock
• Differential clock input
• No Wrtie-Interrupted by Read Function
• 4 DQS’s ( 1DQS / Byte )
• Data I/O transactions on both edges of Data strobe
• DLL aligns DQ and DQS transitions with Clock transition
• Edge aligned data & data strobe output
• Center aligned data & data strobe input
• DM for write masking only
• Auto & Self refresh
• 32ms refresh period (4K cycle)
• 144-Ball FBGA
• Maximum clock frequency up to 300MHz
• Maximum data rate up to 600Mbps/pin

TAG bit, Data, DLL, DRAM, Rate, Strobe

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General Description
The MAX3080E–MAX3089E are ±15kV electrostatic discharge (ESD)-protected, high-speed transceivers for RS- 485/RS-422 communication that contain one driver and one receiver. These devices feature fail-safe circuitry, which guarantees a logic-high receiver output when the receiver inputs are open or shorted. This means that the receiver output will be a logic high if all transmitters on a terminated bus are disabled (high impedance).
 The MAX3080E/MAX3081E/MAX3082E feature reduced slew-rate drivers that minimize EMI and reduce reflections caused by improperly terminated cables, allowing error-free data transmission up to 115kbps. The MAX3083E/MAX3084E/MAX3085E offer higher driver output slew-rate limits, allowing transmit speeds up to 500kbps. The MAX3086E/MAX3087E/ MAX3088Es’ driver slew rates are not limited, making transmit speeds up to 10Mbps possible. The MAX3089E’s slew rate is selectable between 115kbps, 500kbps, and 10Mbps by driving a selector pin with a single three-state driver. All devices feature enhanced ESD protection. All transmitter outputs and receiver inputs are protected to ±15kV using the Human Body Model.
 These transceivers typically draw 375µA of supply current when unloaded, or when fully loaded with the drivers disabled.

 All devices have a 1/8-unit-load receiver input impedance that allows up to 256 transceivers on the bus. The MAX3082E/MAX3085E/MAX3088E are intended for halfduplex communications, while the MAX3080E/MAX3081E/ MAX3083E/MAX3084E/MAX3086E/MAX3087E are intended for full-duplex communications. The MAX3089E is selectable between half-duplex and full-duplex operation. It also features independently programmable receiver and transmitter output phase via separate pins.

* ESD Protection for RS-485 I/O Pins ±15kV, Human Body Model
* True Fail-Safe Receiver While Maintaining EIA/TIA-485 Compatibility
* Enhanced Slew-Rate Limiting Facilitates
  -Error-Free Data Transmission
* 1nA Low-Current Shutdown Mode (Except
* Pin-Selectable Full/Half-Duplex Operation (MAX3089E)
* Phase Controls to Correct for Twisted-Pair Reversal (MAX3089E)
* Allow Up to 256 Transceivers on the Bus

RS-422/RS-485 Communications
Level Translators
Transceivers for EMI-Sensitive Applications
Industrial-Control Local Area Networks


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* Wide Gain-Bandwidth Product . . . 4.5 MHz
* High Slew Rate . . . 13 V/us
* Fast Settling Time . . . 1.1 us to 0.1%
* Wide-Range Single-Supply Operation 4 V to 44 V
* Wide Input Common-Mode Range Includes Ground (VCC–)
* Low Total Harmonic Distortion . . . 0.02%
* Low Input Offset Voltage . . . 3 mV Max (A Suffix)
* Large Output Voltage Swing
–14.7 V to 14 V (With ±15-V Supplies)
* Large Capacitance Drive Capability 10,000 pF
* Excellent Phase Margin . . . 60°
* Excellent Gain Margin . . . 12 dB
* Output Short-Circuit Protection

Quality, low cost, bipolar fabrication with innovative design concepts are employed for the TL33071/2/4, TL34071/2/4, and TL35071/2/4 series of monolithic operational amplifiers. This series of operational amplifiers offers 4.5 MHz of gain bandwidth product, 13 V/ms slew rate, and fast settling time without the use of JFET device technology. Although this series can be operated from split supplies, it is particularly suited for single-supply operation since the common-mode input voltage range includes ground potential (VCC–). With a Darlington transistor input stage, this series exhibits high input resistance, low input offset voltage, and high gain.
 The all-npn output stage, characterized by no dead-band crossover distortion and large output voltage swing, provides high-capacitance drive capability, excellent phase and gain margins, low open-loop high-frequency output impedance, and symmetrical source/sink ac frequency response. The TL34071/2/4 devices are avaliable in standard or prime performance (A-suffix) grades and are specified over the commercial (0°C to 70°C) temperature range. The TL33071/2/4 devices are available in standard or prime performance (A-suffix) grades and are specified over industrial/vehicular (–40°C to 105°C) temperature range. The TL35071/2/4 devices are avaliable in standard or prime performance (A-suffix) grades and are specified over the military (–55°C to 125°C) temperature range.
 These low-cost amplifiers are available in single, dual, and quad configurations and are pin compatible with the MC33071/2/4, MC34071/2/4, and MC35071/2/4 series of amplifiers. Packaging options include standard plastic DIP and SO packages.

TL34071P TL34072P TL34074N TL33071P TL33072P TL33074N TL35071P TL35072P TL35074N
TL34071AP TL34072AP TL34074AN TL33071AP TL33072AP TL33074AN TL35071AP TL35072AP
TL35074AN TL34071D TL34072D TL34074DW TL33071D TL33072D TL33074DW TL35071D
TL35072D TL35074DW TL34071AD TL34072AD TL34074ADW TL33071AD TL33072AD TL33074ADW
TL35071AD TL35072AD TL35074ADW

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