GENERAL DESCRIPTION
The SAA7345 incorporates the CD signal processing functions of decoding and digital filtering. The device is equipped with on-board SRAM and includes additional features to reduce the processing required in the analog domain.
Supply of this Compact Disc IC does not convey an implied license under any patent right to use this IC in any Compact Disc application.

FEATURES
*Integrated data slicer and clock regenerator
*Digital Phase-Locked Loop (PLL)
*Demodulator and Eight-to-Fourteen Modulation (EFM) decoding
*Subcoding microcontroller serial interface
*Integrated programmable motor speed control
*Error correction and concealment functions
*Embedded Static Random Access Memory (SRAM) for de-interleave and First-In First-Out (FIFO)
*FIFO overflow concealment for rotational shock resistance
*Digital audio interface [European Broadcasting Union (EBU)]
*2 to 4 times oversampling integrated digital filter
*Audio data peak level detection
*Versatile audio data serial interface
*Digital de-emphasis filter
*Kill interface for Digital-to-Analog Converter (DAC) deactivation during digital silence
*Double speed mode
*Compact Disc Read Only Memory (CD-ROM) modes
*A single speed only version is available (SAA7345GP/SS).

SAA7345GP

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Description
The HD66520 is a column driver for liquid crystal dot-matrix graphic display systems. This LSI incorporates 160 liquid crystal drive circuits and a 160 ´ 240 ´ 2-bit bit-map RAM, which is suitable for LCDs in portable information devices. It also includes a general-purpose SRAM interface so that draw access can be easily implemented from a general-purpose CPU. The HD66520 also has a new arbitration method which prevents flicker when the CPU performs draw access asynchronously. The on-chip display RAM greatly decreases power consumption compared to previous liquid crystal display systems because there is no need for high-speed data transfer. The chip also incorporates a four-level grayscale controller for enhanced graphics capabilities, such as icons on a screen.

Features
*Duty cycle: 1/64 to 1/240
*Liquid crystal drive circuits: 160
*Low-voltage logic circuit: 3.0 to 5.5-V operation power supply voltage
*High-voltage liquid crystal drive circuit: 8 to 28-V liquid crystal drive voltage
*Grayscale display: FRC four-level grayscale display
*Grayscale memory management: Packed pixel
*Internal bit-map display RAM: 76800 bits (160 ´ 240 lines ´ two planes)
*CPU interface
-SRAM interface
-Address bus: 16 bits, data bus: 8 bits

HD66520TA0, HD66520TB0

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General Description
HT1625 is a peripheral device specially designed for I/O type MCU used to expand the display capability. The max. display segment of the device are 512 patterns (648). It also supports serial interface, buzzer sound, Watchdog Timer or time base timer functions. The HT1625 is a memory mapping and multi-function LCD controller. The software configuration feature of the HT1625 make it suitable for multiple LCD applications including LCD modules and display subsystems. Only three lines are required for the interface between the host controller and the HT1625. The HT162X series have many kinds of products that match various applications.

Features
*Operating voltage: 2.7V~5.2V
*Built-in RC oscillator
*External 32.768kHz crystal or 32kHz frequency source input
*1/4 bias, 1/8 duty, frame frequency is 64Hz
*Max. 648 patterns, 8 commons, 64 segments
*Built-in internal resistor type bias generator
*3-wire serial interface
*8 kinds of time base or WDT selection
*Time base or WDT overflow output
*Built-in LCD display RAM
*R/W address auto increment
*Two selectable buzzer frequencies (2kHz or 4kHz)
*Power down command reduces power consumption
*Software configuration feature
*Data mode and Command mode instructions
*Three data accessing modes
*VLCD pin to adjust LCD operating voltage
*Cascade application
*100-pin QFP package

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Description
The SAE 81C52 is a CMOS-silicon gate, static random access memory (RAM), organized as 256 words by 8 bits. The multiplexed address and data bus interfaces directly to 8-bit microprocessors/microcontrollers without any timing or level problems, e.g. the families SAB 8086, SAB 8051.
All inputs and outputs are fully compatible with NMOS circuits, except CS1. Data retention is ensured up to VDD ³ 1.0 V. The SAE 81C52 has three different inputs for two chip select modes which allow to inhibit either the address/data lines (AD 0 … AD 7) and the control lines (WR, RD, ALE, CS2, CS3), or only the control lines RD, WR.
The power consumption is max. 5.5 mW in standby mode and max. 16.5 mW in operation. In standby mode, the power consumption will not increase if the control inputs are on undefined potential.

PFeatures
*256 x 8-bit organization
*Standby mode
*Compatible with the NMOS and CMOS versions of the microprocessor/microcontroller families
SAB 8086, SAB 8051
*Very low power dissipation
*Data retention up to VDD ³ 1 V
*Three different chip select inputs for two chip select modes
*No increasing power consumption in standby mode if the control inputs are on undefined potential
*Temperature range – 40 to 110 °C

SAE81C52P, SAE81C52G

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GENERAL DESCRIPTION
The 32K x 8 Radiation Hardened Static RAM is a high performance 32,768 x 8-bit static random access memory with industry-standard functionality. It is fabricated with Honeywell’s radiation hardened technology, and is designed for use in systems operating in radiation environments.
The RAM operates over the full military temperature range and requires only a single 5 V ± 10% power supply.
The RAM is available with either TTL or CMOS compatible I/O. Power consumption is typically less than 50 mW/MHz in operation, and less than 5 mW/MHz in the low power disabled mode. The RAM read operation is fully asynchronous, with an associated typical access time of 20 ns.
Honeywell’s enhanced RICMOS™IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. The RICMOS™ IV process is a 5-volt, twin-well CMOS technology with a 170 Å gate oxide and a minimum drawn feature size of 0.8 μm (0.65 μm effective gate length—Leff). Additional features include a three layer interconnect metalization and a lightly doped drain (LDD) structure for improved short channel reliability. High resistivity cross-coupled polysilicon resistors have been incorporated for single event upset hardening.

FEATURES
RADIATION
*Fabricated with RICMOS™ IV Bulk 0.8 μm Process (Leff = 0.65 μm)
*Total Dose Hardness through 1x106 rad(SiO2)
*Neutron Hardness through 1x1014 cm-2
*Dynamic and Static Transient Upset Hardness through 1x109 rad(Si)/s
*Soft Error Rate of <1x10-10 upsets/bit-day
*Dose Rate Survivability through 1x1012 rad(Si)/s
*Latchup Free
OTHER
*Listed on SMD #5962-92153. Available as MIL-PRF-38535 QML Class Q and Class V
*Read/Write Cycle Times ≤ 30 ns (Typical), ≤ 40 ns (-55 to 125°C)
*Standby Current of 20 μA (typical)
*Asynchronous Operation
*CMOS or TTL Compatible I/O
*Single 5 V ± 10% Power Supply
*Packaging Options
- 36-Lead Flat Pack (0.630 in. x 0.650 in.)
- 28-Lead Flat Pack (0.530 in. x 0.720 in.)
- 28-Lead DIP, MIL-STD-1835, CDIP2-T28

HC6856WVRZC35, HC6856WVRZC40, HC6856WVRZC60
TAG RAM

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GENERAL DESCRIPTION
The 128K x 8 Radiation Hardened Static RAM is a high performance 131,072 word x 8-bit static random access memory with industry-standard functionality.
It is fabricated with Honeywell’s radiation hardened technology, and is designed for use in systems operating in radiation environments.
The RAM operates over the full military temperature range and requires only a single 5 V ± 10% power supply.
The RAM is wire bond programmable for either TTL or CMOS compatible I/O.
Power consumption is typically less than 25 mW/MHz in operation, and less than 5 mW in the low power disabled mode.
The RAM read operation is fully asynchronous, with an associated typical access time of 15 ns at 5V.
Honeywell’s enhancedSOI RICMOS™IV (Radiation Insensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout and process hardening techniques.
The RICMOS™ IV process is an advanced 5-volt, SIMOX CMOS technology with a 150 Å
gate oxide and a minimum feature size of 0.7 μm (0.55 μm effective gate length—Leff).
Additional features include Honeywell’s proprietary SHARP planarization process, and a lightly doped drain (LDD) structure for improved short channel reliability.
A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and the low collection volume SIMOX substrate provide improved dose rate hardening.

FEATURES
*RADIATION
-Fabricated with RICMOS™ IV Silicon on Insulator (SOI) 0.7 μm Process (Leff = 0.55 μm)
-Total Dose Hardness through 1x106 rad(SiO2)
-Neutron Hardness through 1x1014 cm-2
-Dynamic and Static Transient Upset Hardness through 1x1011 rad (Si)/s
-Dose Rate Survivability through <1x1012 rad(Si)/s
-Soft Error Rate of <1x10-10 upsets/bit-day in Geosynchronous Orbit
-No Latchup
*OTHER
-Read/Write Cycle Times
 ≤ 16 ns (Typical)
 ≤ 25 ns (-55 to 125°C)
-Typical Operating Power <25 mW/MHz
-Asynchronous Operation
-CMOS or TTL Compatible I/O
-Single 5 V ± 10% Power Supply
-Packaging Options
 32-Lead Flat Pack (0.820 in. x 0.600 in.)
 40-Lead Flat Pack (0.775 in. x 0.710 in.)

HX6228AVRC
HX6228KQFT
TAG RAM

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The P10C68 and P11C68 are fast static RAMs (35 and 45 ns) with a non-volatile electically-erasable PROM (EEPROM) cell incorporating in each static memory cell. The SRAM can be read and written an unlimited number of times while independent non-volatile data resides in PROM.
On the P10C68 data may easily be transferred from the SRAM to the EEPROM (STORE) and from the EEPROM back the SRAM ( RECALL) using the NE (bar) pin. The Store and
Recall cycles are initiated through software sequences on the P11C68. These devices combine the high performance and ease of use of a fast SRAM with the data integrity of nonvolatility.
The P10C68 and P11C68 feature the industry standard pinout for non-volatile RAMs in a 28-pin 0.3-inch plastic and ceramic dual-in-line packages.

FEATURES
* Non-Volatile Data Integrity
* 10 year Data Retention in EEPROM
* 35ns and 45ns Address and Chip Enable Access Times
* 20ns and 25ns Output Enable Access
* Unlimited Read and Write to SRAM
* Unlimited Recall Cycles from EEPROM
* 104 Store Cycles to EEPROM
* Automatic Recall on Power up
* Automatic Store Timing
* Hardware Store Protection
* Single 5V * 10% Operation
* Available in Standard Package 28-pin 0.3-inch DIL plastic and ceramic
* Commercial and Industrial temperature ranges


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Features
• 4.5V-5.5V operation
• CMOS for optimum speed/power
• Low active power
-660 mW (max.)
• Low standby power (L version)
-2.75 mW (max.)
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE and OE options

Functional Description
The CY62148 is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW
output enable (OE), and three-state drivers. This device has an automatic power-down feature that reduces power consumption by more than 99% when deselected.
Writing to the device is accomplished by taking chip enable one (CE) and write enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location
specified on the address pins (A0 through A18).
Reading from the device is accomplished by taking chip enable one (CE) and output enable (OE) LOW while forcing write enable (WE). Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins.
The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write
operation (CE LOW, and WE LOW).
The CY62148 is available in a standard 450-mil-wide body width SOIC package.

CY62148-55SC
CY62148L-55SC
CY62148-70SC
CY62148L-70SC
CY62148-70SI
CY62148L-70SI

TAG RAM, Static

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FEATURES
•Nonvolatile Storage without Battery Problems
•Directly Replaces 8K x 8 Static RAM, Battery- Backed RAM or EEPROM
•25ns, 35ns and 45ns Access Times
•STORE to Nonvolatile Elements Initiated by Software or AutoStore™ on Power Down
•RECALL to SRAM Initiated by Software or Power Restore
•10mA Typical ICC at 200ns Cycle Time
•Unlimited READ, WRITE and RECALL Cycles
•1,000,000 STORE Cycles to Nonvolatile Elements
•100-Year Data Retention over Full Industrial Temperature Range
•No Data Loss from Undershoot
•Commercial and Industrial Temperatures
•28-Pin 600 or 300 mil PDIP and 350 mil SOIC Packages

DESCRIPTION
The STK15C68 is a fast SRAM with a nonvolatile element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in Nonvolatile Elements. Data transfers from the SRAM to the Nonvolatile Elements (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the Nonvolatile Elements to the SRAM (the RECALL operation) take place automatically on restoration of power. Initiation of STORE and RECALL cycles can also be controlled by entering control sequences on the SRAMinputs. The STK15C68 is pin-compatible with 8k x 8 SRAMs and battery-backed SRAMs, allowing direct substitution while enhancing performance. A similar device (STK16C68) with an internally integrated capacitor is available for systems with very fast slew rates. The STK12C68, which uses an external capacitor, is an alternative for these applications.



STK15C68-PF45I
STK15C68-PF25I
STK15C68-PF35I


TAG CMOS, QUANTUM, RAM, SRAM

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Features
- Organization: 262,144 words X 16 bits
- Part Identification
- A418316 (512 Ref.)
- Single 5.0V power supply/built-in VBB generator
- Low power consumption
- Operating: 110mA (-25 max)
- Standby: 2.5mA (TTL), 1.0mA (CMOS) 1.0mA (Self-refresh current)
- High speed
- 25/35 ns RAS access time
- 12/17 ns column address access time
- 8/10 ns CAS access time
- 15/19 ns FAST Page Mode Cycle Time
- Industrial operating temperature range: -40°C to 85°C for -U
- Separate CAS (UCAS ,LCAS ) for byte selection
- 512 Refresh Cycle in 8ms
- Read-modify-write, RAS -only, CAS -before- RAS , Hidden refresh capability
- TTL-compatible, three-state I/O
- JEDEC standard packages
- 400mil, 40-pin SOJ
- 400mil, 40/44 TSOP type II package

General Description
The A418316 is a new generation randomly accessed memory for graphics, organized in a 262,144-word by 16- bit configuration. This product can execute Byte Write and Byte Read operation via two CAS pins.
The A418316 offers an accelerated Fast Page Mode This allow random access of up to 512 words within a row at a 66/52 MHz FAST cycle, making the A418316 ideally suited for graphics, digital signal processing and high performance computing systems.

A418316S-25
A418316S-35
A418316V-25
A418316V-35
A418316V-25U
A418316V-35U

TAG CMOS, RAM

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