General Description
Quad Low-Side Switch in Smart Power Technology (SPT) with a Serial Peripheral Interface (SPI) and four open drain DMOS output stages. The TLE 6220 GP is protected by embedded protection functions and designed for automotive and industrial applications. The output stages can be controlled direct in parallel for PWM applications (injector coils), or through serial control via the SPI. Therefore the TLE 6220 GP is particularly suitable for engine management and powertrain systems.

*Short Circuit Protection
*Overtemperature Protection
*Overvoltage Protection
*8 bit Serial Data Input and Diagnostic Output (SPI protocol)
*Direct Parallel Control of Four Channels for PWM Applications
*Cascadable with Other Quad Switches
*Low Quiescent Current
*μC Compatible Input
*Electostatic Discharge (ESD) Protection

*μC Compatible Power Switch for 12 V and 24 V Applications
*Switch for Automotive and Industrial System
*Solenoids, Relays and Resistive Loads
*Robotic controls


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The VNQ5E160K-E is a quad channel high-side driver manufactured in the ST proprietary VIPower M0-5 technology and housed in the tiny PowerSSO-24 package.
The VNQ5E160K-E is designed to drive automotive grounded loads delivering protection, diagnostics and easy 3V and 5V CMOS-compatible interface with any microcontroller.
The device integrates advanced protective functions such as load current limitation, inrush and overload active management by power limitation, over-temperature shut-off with auto-restart and over-voltage active clamp.
A dedicated active low digital status pin is associated with every output channel in order to provide Enhanced diagnostic functions including fast detection of overload and short-circuit to ground, over-temperature indication, short-circuit to VCC diagnosis and ON & OFF state open-load detection.
The diagnostic feedback of the whole device can be disabled by pulling the STAT_DIS pin up, thus allowing wired-ORing with other similar devices.

– Inrush current active management by power limitation
– Very low stand-by current
– 3.0V CMOS compatible inputs
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC european directive
*Diagnostic functions
– Open Drain status output
– On-state open load detection
– Off-state open load detection
– Output short to VCC detection
– Overload and short to ground (power limitation) indication
– Thermal shutdown indication
– Undervoltage shutdown
– Overvoltage clamp
– Load current limitation
– Self limiting of fast thermal transients
– Protection against loss of ground and loss of VCC
– Over-temperature shutdown with autorestart (thermal shutdown)
– Reverse battery protected

*All types of resistive, inductive and capacitive loads

TAG Quad

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The MC54/74HC4066A utilizes silicon–gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF–channel leakage current. This bilateral switch/multiplexer/demultiplexer controls analog and digital voltages that may vary across the full power–supply range (from VCC to GND).
The HC4066A is identical in pinout to the metal–gate CMOS MC14016 and MC14066. Each device has four independent switches. The device has been designed so that the ON resistances (RON) are much more linear over input voltage than RON of metal–gate CMOS analog switches.
The ON/OFF control inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
For analog switches with voltage–level translators, see the HC4316A.

*Fast Switching and Propagation Speeds
*High ON/OFF Output Voltage Ratio
*Low Crosstalk Between Switches
*Diode Protection on All Inputs/Outputs
*Wide Power–Supply Voltage Range (VCC – GND) = 2.0 to 12.0 Volts
*Analog Input Voltage Range (VCC – GND) = 2.0 to 12.0 Volts
*Improved Linearity and Lower ON Resistance over Input Voltage than the MC14016 or MC14066
*Low Noise
*Chip Complexity: 44 FETs or 11 Equivalent Gates


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The Intersil ISL32x7xE are ±16.5kV IEC61000-4-2 ESD Protected, 3.0V to 5.5V powered, QUAD transmitters for balanced communication using the RS-422 standard. These drivers have very low output leakage currents (±10μA), so they present a low load to the RS-422 bus.
Driver (Tx) outputs are tri-statable, and incorporate a hot plug feature to keep them disabled during power-up and down. Versions are available with a common EN/EN (‘172 pinout), a two channel EN12/EN34 (‘174 pinout), or a versatile combination of individual and group channel
The ISL32372E, ISL32374E utilize slew rate limited drivers which reduce EMI, and minimize reflections from improperly terminated transmission lines, or from unterminated stubs in multidrop and multipoint applications. Drivers on the other versions are not limited, so they can achieve the 10Mbps or 32Mbps data rates. All versions are offered in Industrial and Extended Industrial (-40°C to +125°C) temperature ranges.
A 50% smaller footprint (compared to the TSSOP) is available with the ISL32179E’s QFN package. This device also features a logic supply pin (VL), that sets the switching points of the enable and DI inputs to be compatible with a lower supply voltage in mixed voltage systems. Two speed select pins allow the ISL32179E user to select from three slew rate options for 460kbps, 10Mbps, or 32Mbps data rates. Individual channel and group enable pins increase the ISL32179E’s flexibility.

*IEC61000 ESD Protection on RS-422 Outputs . . ±16.5kV
- Class 3 ESD Level on all Other Pins . . . . . . 12kV HBM
- High Machine Model ESD Level on all Pins . . . . . 700V
*Wide Supply Range . . . . . . . . . . . . . . . . . . . 3.0V to 5.5V
*Specified for +125°C Operation
*Available in Industry Standard Pinouts (‘172/’174) or in a Space Saving QFN (ISL32179E) with Added Features
*Logic Supply Pin (VL) Eases Operation in Mixed Supply Systems (ISL32179E Only)
*User Selectable Data Rate (ISL32179E Only)
*Hot Plug - Tx Outputs Remain Three-state During Power-up and Power-Down
*Low Tx Leakage Allows > 256 Devices on the Bus
*High Data Rates. . . . . . . . . . . . . . . . . . . . . up to 32Mbps
*Low Quiescent Supply Current . . . . . . . . . . 0.8mA (Max)
- Low Shutdown Supply Current . . . . . . . . . . . . . . . 60μA
*Current Limiting and Thermal Shutdown for Driver Overload Protection
*Tri-statable Tx Outputs
*5V Tolerant Logic Inputs When VCC ≤ 5V
*Pb-free (RoHS compliant)

*Telecom Equipment
*Motor Controllers / Encoders
*Programmable Logic controllers
*Industrial/Process Control Networks

ISL32272E, ISL32372E, ISL32174E, ISL32274E, ISL32374E, ISL32179E

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The ADM1184 is an integrated, 4-channel voltage-monitoring device. A 2.7 V to 5.5 V power supply is required on the VCC pin to power the device.
Four precision comparators monitor four voltage rails. Each comparator has a 0.6 V reference with a worst-case accuracy of 0.8%. Resistor networks that are external to the VIN1, VIN2, VIN3, and VIN4 pins set the trip points for the monitored supply rails.
The ADM1184 has four open-drain outputs. OUT1 to OUT3 can be used to enable power supplies, and PWRGD is a common power-good output.
OUT1 to OUT3 are dependent on their associated VINx input (that is, VIN1, VIN2, or VIN3). If a supply monitored by VINx drops below its programmed threshold, the associated OUTx pin and PWRGD are disabled.
PWRGD is a common power-good output indicating the status of all monitored supplies. There is an internal 190 ms (typical) delay associated with the assertion of the PWRGD output. If VIN1, VIN2, VIN3, or VIN4 drops below its programmed threshold, PWRGD is deasserted immediately.
The ADM1184 is available in a 10-lead mini small outline package (MSOP).

*Powered from 2.7 V to 5.5 V on the VCC pin
*Monitors 4 supplies via 0.8% accurate comparators
*4 inputs can be programmed to monitor different voltage levels with external resistor dividers
*3 open-drain enable outputs (OUT1, OUT2, and OUT3)
*Open-drain power-good output (PWRGD)
*Internal 190 ms delay associated with assertion of PWRGD
*10-lead MSOP

*Monitor and alarm functions
*Microprocessor systems


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The DS1844 Quad Digital Potentiometer is a four-channel, digitally controlled linear potentiometer.
Each potentiometer is comprised of 63 equi-resistive sections and has three terminals accessible to the user.
These include the high side terminals, HX, the wiper terminals, WX, and the low-side terminals, LX.
The wiper position on the resistor ladder is selected via an 8-bit register value.
Communication and control of the device are supported by two types of serial interface.
These include a 5-wire I/O shift register interface and a 2-wire addressable interface.
The DS1844 is available in standard 10 k, 50 k, and 100 k versions.
Mixed resistor combinations are also available through custom setups.
The DS1844 is specified to operate over the industrial temperature range: -40C to +85C.
Packages for the DS1844 include 20-pin DIPs, SOICs, and TSSOPs.

* Four independent, digitally controlled 64-position potentiometers
* Two interface control options
- 5-wire serial
- 2-wire addressable
* Standard resistance values
- DS1844-010 10 k
- DS1844-050 50 k
- DS1844-100 100 k
* Mixed resistor value combinations (contact factory for availability)
* Operating Temperature Range
- Industrial: -40°C to +85°C

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 The function of the S3029 clock synthesis and recovery unit is to derive high speed timing signals for SONET/SDH-based equipment.
The S3029 is implemented using AMCC’s proven Phase Locked Loop (PLL) technology.
The S3029 receives four STS-3/STM-1 scrambled NRZ signals and recovers the clock from the data and generates a 155 MHz transmit clock.
The chip outputs a differential PECL bit clock and retimed data.
Figure 1 shows a typical network application.
The S3029 utilizes five on-chip PLLs which consist of a phase detector, a loop filter, and a voltage controlled oscillator (VCO).
The phase detector compares the phase relationship between the VCO output and the serial data input.
A loop filter converts the phase detector output into a smooth DC voltage, and the DC voltage is input to the VCO whose frequency is varied by this voltage.
A block diagram is shown in Figure 2.
There is a single clock multiplier PLL which generates a 155 MHz transmit clock from a 19.44 or 51.84 MHz input.

* Complies with ANSI, Bellcore, and ITU-T specifications for jitter tolerance, jitter generation
* Five on-chip high frequency PLLs with internal loop filters for clock recovery
* Supports clock recovery for STS-3/STM-1 (155.52 Mbit/s) NRZ data
* Clock Multiplier PLL for transmit clock generation
* 19.44 or 51.84 MHz reference frequency
* Lock detect—monitors run length and frequency
* Low-jitter differential interface
* 3.3V supply
* Available in a 64-pin TQFP package
* Compatible with IgT WAC-413 ATM Quad- UNI processor


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The Intersil ISL84467 device is a low ON-resistance, low voltage, bidirectional, Quad SPDT (Dual DPDT) analog switch designed to operate from a single +1.65V to +4.5V supply.
Targeted applications include battery powered equipment that benefit from low rON (0.39Ω) and fast switching speeds (tON = 33ns, tOFF = 16ns).
The digital logic input is 1.8V logic-compatible when using a single +3V supply.
With a supply voltage of 4.2V and logic high voltage of 2.85V at both logic inputs, the part draws only 12μA max of ICC current.
Cell phones, for example, often face ASIC functionality limitations.
The number of analog input or GPIO pins may be limited and digital geometries are not well suited to analog switch performance.
This part may be used to “mux-in” additional functionality while reducing ASIC design risk.
The ISL84467 is offered in small form factor package, alleviating board space limitations.
The ISL84467 consists of four SPDT switches.
It is configured as a dual double-pole/double-throw (DPDT) device with two logic control inputs that control two SPDT switches each.
The configuration can be used as a dual differential 2-to-1 multiplexer/demultiplexer.

• ON-Resistance (rON)
- V+ = +4.3V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.39Ω
- V+ = +3.0V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.45Ω
- V+ = +1.8V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.65Ω
• rON Matching Between Channels . . . . . . . . . . . . . . 0.05Ω
• rON Flatness Across Signal Range . . . . . . . . . . . . . 0.05Ω
• Single Supply Operation . . . . . . . . . . . . . . +1.65V to +4.5V
• Low Power Consumption (PD) . . . . . . . . . . . . . . <0.68μW
• Fast Switching Action (V+ = +4.3V)
- tON  . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33ns
- tOFF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16ns
• Break-Before-Make
• 1.8V Logic Compatible (+3V supply)
• Low ICC Current when VinH is not at the V+ Rail
• Available in 16 Ld 3x3 TQFN
• ESD HBM Rating
- COM Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9kV
- All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6kV
• Pb-Free Plus Anneal Available (RoHS Compliant)

• Battery-Powered, Handheld, and Portable Equipment
- Cellular/Mobile Phones
- Pagers
- Laptops, Notebooks, Palmtops
• Portable Test and Measurement
• Medical Equipment
• Audio and Video Switching

Related Literature
• Technical Brief TB363 “Guidelines for Handling and Processing Moisture Sensitive Surface Mount Devices (SMDs)”
• Application Note AN557 “Recommended Test Procedures for Analog Switches”


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· >400 Mbps (200 MHz) Signaling Rates
· Flow-Through Pinout Simplifies PCB Layout
· 300 ps Maximum Differential Skew
· Propagation Delay Times 1.8 ns (Typical)
· 3.3 V Power Supply Design
· ±350 mV Differential Signaling
· High Impedance on LVDS Outputs on Power Down
· Conforms to TIA/EIA-644 LVDS Standard
· Industrial Operating Temperature Range (-40°C to 85°C)
· Available in SOIC and TSSOP Packages

The SN65LVDS047 is a quad differential linedriver that implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the four current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-W load when enabled.
The intended application of this device and signaling technique is for point-to-point and multi-drop baseband data transmission over controlled impedance media of approximately 100 W. The ransmission media may be printed-circuit board traces, backplanes, or cables. The ultimate rate and  distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.

TAG Driver, LVDS, Quad

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■ ICC and IOZ reduced by 50%
■ Multiplexer expansion by tying outputs together
■ Inverting 3-STATE outputs
■ Outputs source/sink 24mA
■ TTL-compatible inputs

General Description
 The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form.
 The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.

Functional Description
The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the I
0x inputs are selected and when Select is HIGH, the I1x inputs are selected.
 The data on the selected inputs appears at the outputs in inverted form. The ACT258 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:
Za= OE • (I1a • S + I0a • S)
Zb= OE • (I1b • S + I0b • S)
Zc= OE • (I1c • S + I0c • S)
Zd= OE • (I1d • S + I0d • S)
When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings.
 Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap.


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