'QPSK' related articles 1

  1. 2006/08/10 STV0299B - QPSK/BPSK LINK IC
DESCRIPTION
The STV0299 Satellite Receiver with FEC is a CMOS single-chip multistandard demodulator for
digital satellite broadcasting. It consists of two A/D converters for I-input and Q-input, a multistandard QPSK and BPSK demodulator, and a forward error correction (FEC) unit having both an inner (Viterbi) and outer (Reed-Solomon) decoder.
The FEC unit is compliant with the DVB-S and DSSTM specifications. Processing is fully digital.
It integrates a derotator before the Nyquist root filter, allowing a wide range of offset tracking.
The high sampling rate facilitates the implementation of low-cost, direct conversion tuners.
A variety of configurations and behaviours can be selected through a bank of control / configuration registers via an I2C. The chip outputs MPEG Transport Streams and interfaces seamlessly to the Packet Demultiplexers embedded in ST’s ST20-TPx or STi55xx. High sampling frequency (up to 90MHz) considerably reduces the cost of LPF of direct conversion tuners.
The multistandard capability associated with a broad range of input frequency operations makes
it easy-to-use. Its low power consumption, small package and optional serial output interface
makes it perfect for embedding into a tuner.

FEATURE
■ MULTISTANDARD QPSK AND BPSK DEMODULATION
■ EASY IMPLEMENTATION WITH LOW COST DIRECT CONVERSION TUNERS
■ EXTREMELY LOW BER WHEN CO-CHANNEL INTERFERENCE
■ WIDE CARRIER LOOP TRACKING RANGE TO COMPENSATE FOR DISH FREQUENCY DRIFT
■ COMMON INTERFACE COMPLIANT
■ VERY LOW POWER CONSUMPTION
■ INTEGRATED DUAL 6-BIT ANALOG TO DIGITAL CONVERTERS
■ DUAL DIGITAL AGC
■ DIGITAL NYQUIST ROOT FILTER WITH ROLL-OFF OF 0.35 OR 0.20
■ DIGITAL CARRIER LOOP WITH LOCK DETECTOR, ON-CHIP WIDE RANGE DEROTATOR AND TRACKING LOOP (TYP ± 45 MHz)
■ DIGITAL TIMING RECOVERY WITH LOCK DETECTOR
■ CHANNEL BIT RATE UP TO 90 Mbps AND SYMBOL FREQUENCY RATE FROM 1 TO 50 M SYMBOLS
■ INNER DECODER:
  - VITERBI SOFT DECODER FOR CONVOLUTIONAL CODES, M=7, RATE 1/2
  - PUNCTURED CODES 1/2, 2/3, 3/4, 5/6, 6/7 AND 7/8
■ SYNCHROWORD EXTRACTION
■ CONVOLUTIVE DEINTERLEAVER
■ OUTER DECODER:
  - REED-SOLOMON DECODER FOR 16 PARITY BYTES; CORRECTION OF UP TO 8 BYTE ERRORS
  - ENERGY DISPERSAL DESCRAMBLER
■ ON-CHIP FLEXIBLE CLOCK SYSTEMS TO ALLOW USE OF EXTERNAL CLOCK SIGNALS IN 4 MHz TO 30 MHz RANGE
■ EASY-TO-USE C/N ESTIMATOR WITH 2 TO 18 dB RANGE
■ I2C SERIAL BUS AND REPEATER
■ DVB COMMON INTERFACE COMPLIANT PARALLEL OUTPUT FORMAT
■ PARALLEL AND SERIAL DATA OUTPUT
■ LNB SUPPLY CONTROL WITH STANDARD I/O, 22 KHz TONE AND DISEQCTM MODULATOR
WITH TTL OUTPUT
■ CMOS TECHNOLOGY: 2.5 V OPERATION; JEDEC (EIA/JESD8-5)
TAG , ,

Trackback :: http://datasheetblog.com/trackback/141

댓글을 달아 주세요 Comment