Description
Xilinx introduces the Platform Flash series of in-system programmable configuration PROMs. Available in 1 to 32 Megabit (Mbit) densities, these PROMs provide an easy-touse, cost-effective, and reprogrammable method for storing large Xilinx FPGA configuration bitstreams. The Platform Flash PROM series includes both the 3.3V XCFxxS PROM and the 1.8V XCFxxP PROM. The XCFxxS version includes 4-Mbit, 2-Mbit, and 1-Mbit PROMs that support Master Serial and Slave Serial FPGA configuration modes. The XCFxxP version includes 32-Mbit,
16-Mbit, and 8-Mbit PROMs that support Master Serial, Slave Serial, Master SelectMAP, and Slave SelectMAP FPGA configuration modes. A summary of the Platform Flash PROM family members and supported features is shown in Table 1.

Features
*In-System Programmable PROMs for Configuration of Xilinx® FPGAs
*Low-Power Advanced CMOS NOR Flash Process
*Endurance of 20,000 Program/Erase Cycles
*Operation over Full Industrial Temperature Range (–40°C to +85°C)
*IEEE Standard 1149.1/1532 Boundary-Scan (JTAG) Support for Programming, Prototyping, and Testing
*JTAG Command Initiation of Standard FPGA Configuration
*Cascadable for Storing Longer or Multiple Bitstreams
*Dedicated Boundary-Scan (JTAG) I/O Power Supply (VCCJ)
*I/O Pins Compatible with Voltage Levels Ranging From 1.5V to 3.3V
*Design Support Using the Xilinx Alliance ISE® and Foundation™ ISE Series Software Packages
*XCF01S/XCF02S/XCF04S
-3.3V Supply Voltage
-Serial FPGA Configuration Interface (up to 33 MHz)
-Available in Small-Footprint VO20 and VOG20 Packages
*XCF08P/XCF16P/XCF32P
-1.8V Supply Voltage
-Serial or Parallel FPGA Configuration Interface(up to 33 MHz)
-Available in Small-Footprint VO48, VOG48, FS48, and FSG48 Packages
-Design Revision Technology Enables Storing and Accessing Multiple Design Revisions for
Configuration
-Built-In Data Decompressor Compatible with Xilinx Advanced Compression Technology

XCF02S, XCF04S, XCF08P, XCF16P, XCF32P

Trackback :: http://datasheetblog.com/trackback/2265

댓글을 달아 주세요 Comment

Product Features
*IEEE 802.3 10BASE-T/100BASE-TX compliant physical layer interface
*IEEE 802.3u Auto-Negotiation support
*Digital Adaptive Equalization control
*Link status interrupt capability
*XOR tree mode support
*3-port LED support (speed, link and activity)
*10BASE-T auto-polarity correction
*LAN Connect Interface
*Diagnostic loopback mode
*1:1 transmit transformer ratio support
*Low power (less than 300 mW in active transmit mode)
*Reduced power in “unplugged mode” (less than 50 mW)
*Automatic detection of “unplugged mode”
*3.3 V device
*48-pin Shrink Small Outline Package

Trackback :: http://datasheetblog.com/trackback/1887

댓글을 달아 주세요 Comment

Description
 The AT97SC3203S is a fully integrated security module designed to be integrated into embedded systems.
It implements version 1.2 of the Trusted Computing Group (TCG) specification for Trusted Platform Modules (TPM).
The TPM includes a cryptographic accelerator capable of computing a 2048-bit RSA signature in 500 ms and a 1024-bit RSA signature in 100 ms.
Performance of the SHA-1 accelerator is 50 μs per 64-byte block.
In most cases, TCG key generation operations will be completed using a proprietary mechanism in less than 1 msec.
Communication to and from the TPM occurs through a modified 100-kHz SMBus two-wire interface.
The TPM includes a hardware random number generator, including a FIPS-approved Pseudo Random Number Generator, that is used for key generation and TCG protocol functions.
The RNG is also available to the system to generate random numbers that may be needed during normal operation.
The chip uses a dynamic internal memory management scheme to store multiple RSA keys.
Other than the standard TCG commands (TPM_FlushSpecific, TPM_Loadkey2), no system
intervention is required to manage this internal key cache.
This specification includes only mechanical, electrical and SMBus protocol information.

Features
• Full Trusted Computing Group (TCG) Trusted Platform Module (TPM) Version 1.2 Compatibility
• Single-chip Turnkey Solution
• Hardware Asymmetric Crypto Engine
• 2048-bit RSA® Sign in 500 ms
• AVR® RISC Microprocessor
• Internal EEPROM Storage for RSA Keys
• 100 kHz System Management Bus (SMBus™) Two-wire Interface
• Secure Hardware and Firmware Design and Chip Layout
• True Random Number Generator (RNG) - FIPS 140-2 Compliant
• NV Storage Space for 1280 bytes of user defined data
• 3.3V Supply Voltage
• 28-lead TSSOP Package or 40-lead QFN Package
• 0–70°C Temperature Range

Trackback :: http://datasheetblog.com/trackback/1544

댓글을 달아 주세요 Comment