GENERAL DESCRIPTION
The S2042 and S2043 transmitter and receiver pair are designed to perform high-speed serial data transmission over fiber optic or coaxial cable interfaces conforming to the requirements of the ANSI X3T11 Fibre Channel specification. The chipset is selectable to 1062, 531 or 266 Mbit/s data rates with associated 10- or 20-bit data word.
The chipset performs parallel-to-serial and serial-toparallel conversion and framing for block-encoded data. The S2042 on-chip PLL synthesizes the highspeed clock from a low-speed reference. The S2043 on-chip PLL synchronizes directly to incoming digital signals to receive the data stream. The transmitter and receiver each support differential PECL-compatible I/O for fiber optic component interfaces, to minimize crosstalk and maximize data integrity. Local loopback allows for system diagnostics. The TTL I/O section can operate from either a +3.3V or a +5V power supply. With a 3.3V power supply the chipset dissipates only 1W typically.
Figure 1 shows a typical network configuration incorporating the chipset. The chipset is compatible with AMCC’s S2036 Open Fiber Control (OFC) device.

FEATURES
*Functionally compliant with ANSI X3T11 Fibre Channel physical and transmission protocol standards
*S2042 transmitter incorporates phase-locked loop (PLL) providing clock synthesis from low-speed reference
*S2043 receiver PLL configured for clock and data recovery
*1062, 531 and 266 Mb/s operation
*10- or 20-bit parallel TTL compatible interface
*1 watt typical power dissipation for chipset
*+3.3/+5V power supply
*Low-jitter serial PECL compatible interface
*Lock detect
*Local loopback
*10mm x 10mm 52 PQFP package
*Fibre Channel framing performed by receiver
*Continuous downstream clocking from receiver
*TTL compatible outputs possible with +5V I/O power supply

APPLICATIONS
High-speed data communications
*Supercomputer/Mainframe
*Workstation
*Switched networks
*Proprietary extended backplanes
*Mass storage devices/RAID drives

S2043, S2042B-10, S2043B-10

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Functional Description
The architecture of the XC236x combines advantages of RISC, CISC, and DSP processors with an advanced peripheral subsystem in a very well-balanced way. In addition, the on-chip memory blocks allow the design of compact systems-on-silicon with maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources as well as external resources (see Figure 3). This bus structure enhances the overall system performance by enabling the concurrent operation of several subsystems of the XC236x.
The following block diagram gives an overview of the different on-chip components and of the advanced, high bandwidth internal bus structure of the XC236x.

Summary of Features
For a quick overview or reference, the XC236x’s properties are listed here in a condensed way.
*High Performance 16-bit CPU with 5-Stage Pipeline
– 15 ns Instruction Cycle Time at 66 MHz CPU Clock (Single-Cycle Execution)
– 1-Cycle 32-bit Addition and Subtraction with 40-bit result
– 1-Cycle Multiplication (16 × 16 bit)
– 1-Cycle Multiply-and-Accumulate (MAC) Instructions
– Background Division (32 / 16 bit) in 21 Cycles
– Enhanced Boolean Bit Manipulation Facilities
– Zero-Cycle Jump Execution
– Additional Instructions to Support HLL and Operating Systems
– Register-Based Design with Multiple Variable Register Banks
– Fast Context Switching Support with Two Additional Local Register Banks
– 16 Mbytes Total Linear Address Space for Code and Data
– 1024 Bytes On-Chip Special Function Register Area (C166 Family Compatible)
*16-Priority-Level Interrupt System with up to 79 Sources, Selectable External Inputs for Interrupt Generation and Wake-Up, Sample-Rate down to 15 ns
*8-Channel Interrupt-Driven Single-Cycle Data Transfer Facilities via Peripheral Event Controller (PEC), 24-Bit Pointers Cover Total Address Space
*Clock Generation from Internal or External Clock Sources, via on-chip PLL or via Prescaler
*On-Chip Memory Modules
– 1 Kbyte On-Chip Stand-By RAM (SBRAM)
– 2 Kbytes On-Chip Dual-Port RAM (DPRAM)
– 16 Kbytes On-Chip Data SRAM (DSRAM)
– Up to 32 Kbytes On-Chip Program/Data SRAM (PSRAM)
– Up to 576 Kbytes On-Chip Program Memory (Flash Memory)
*On-Chip Peripheral Modules
– Two Synchronizable A/D Converters with a total of 16 Channels, 10-bit Resolution, Conversion Time down to 1.2 μs, Optional Data Preprocessing (Data Reduction, Range Check)
– 16-Channel General Purpose Capture/Compare Unit (CAPCOM2)
– Two Capture/Compare Units for flexible PWM Signal Generation (CCU6x)
– Multi-Functional General Purpose Timer Unit with 5 Timers
– Six Serial Interface Channels to be used as UART, LIN, High-Speed Synchronous Channel (SPI/QSPI), IIC Bus Interface (10-bit addressing, 400 kbit/s), IIS Interface
– On-Chip MultiCAN Interface (Rev. 2.0B active) with 64 Message Objects (Full CAN/Basic CAN) on 3 CAN Nodes and Gateway Functionality
– On-Chip Real Time Clock
*Up to 12 Mbytes External Address Space for Code and Data
– Programmable External Bus Characteristics for Different Address Ranges
– Multiplexed or Demultiplexed External Address/Data Buses
– Selectable Address Bus Width
– 16-Bit or 8-Bit Data Bus Width
– Four Programmable Chip-Select Signals
*Single Power Supply from 3.0 V to 5.5 V
*Programmable Watchdog Timer and Oscillator Watchdog
*Up to 75 General Purpose I/O Lines
*On-Chip Bootstrap Loader
*Supported by a Large Range of Development Tools like C-Compilers, Macro-Assembler Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards
*On-Chip Debug Support via JTAG Interface
*100-Pin Green LQFP Package, 0.5 mm (19.7 mil) pitch

XC2365

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Description
PBL 3770A is a bipolar monolithic circuit intended to control and drive the current in one winding of a stepper motor. It is a high power version of PBL 3717 and special care has been taken to optimize the power handling capability without suffering in reliability.
The circuit consists of a LS-TTL compatible logic input stage, a current sensor, a monostable multivibrator and a high power H-bridge output stage. The circuit is pin-compatible with the PBL 3717 industry-standard driver.
Two PBL 3770A and a small number of external components form a complete control and drive unit for LS-TTL or microprocessor-controlled stepper motor systems.

Key Features
• Half-step and full-step operation.
• Switched mode bipolar constant current drive
• Wide range of current control 5 -1800 mA.
• Wide voltage range 10 - 45 V.
• Designed for unstabilized moto supply voltage.
• Current levels can be selected in steps or varied continuously.
• Thermal overload protection.

PBL 3770ANS, PBL 3770AQNS, PBL 3770AQNT
PBL 3770ASOS, PBL 3770ASOT

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DESCRIPTION
 Microsemi’s LX6512 is a cost effective, Direct Drive CCFL (Cold Cathode Fluorescent Lamp) controller.
The integrated controller is optimized to drive CCFL’s (Cold Cathode Fluorescent Lamps) using either resonant full bridge inverter topology or push-pull Direct Drive configurations.
Resonant full bridge topology provides near sinusoidal waveforms over a wide supply voltage range in order to maximize the life of CCFL lamps, control EMI emissions, and maximize efficiency.
This new architecture is also coupled with a wide dimming range capability.
For fixed input supply applications the LX6512 uses Direct Drive topology to supply fixed frequency PWM signals connected directly to the high voltage transformer primary via a single pair of NFET drivers, providing a simple, low cost inverter solution.
The LX6512 contains safety features that limit the transformer secondary voltage and protect against fault conditions which include open lamp, broken lamp and short-circuit faults.
The over voltage fault shutdown is disabled during a user programmable interval to allow lamp strike.
The controller can accept a brightness control signal that is either an analog voltage level, or a direct low frequency PWM.
Utilizing this signal it provides CCFL brightness dimming control using digital dimming, to achieve a wide dimming range (> 60 to 1).
An integrated 4V LDO (Low Dropout Regulator) powers all internal control circuitry and up to 5mA for external circuitry greatly simplifying supply voltage requirements.
The LX6512 is available in a 16-Pin TSSOP and 3x3 mm 16pin QFN.

KEY FEATURES
* Full Bridge or Direct Drive Push Pull Configurable
* Patented Striking Topology
* Low Stress to Transformers
* Wide Dimming Range
* Programmable Operating Dimming Frequency
* Programmable Time Out Protection
* Fixed Operating Frequency
* Open Lamp Voltage Protection, Short Lamp Protection, Over Voltage Protection
* Compatible with Existing Transformers

APPLICATIONS
* Note Book LCD displays
* Transportable Computers
* Web Tablet LCD displays
* Digital Picture Frame
* Monitor / TV
* Portable DVD Player

LX6512CLQ
LX6512CPW

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Overview
The nanoNET TRX transceiver is a highly integrated mixed signal chip utilizing the unique wireless communication technology CSS (Chirp Spread Spectrum) developed by Nanotron Technologies. nanoNET TRX allows a high range of up to 900 meters in free space and 60 meters indoors in the 2.45 GHz ISM band (@ 1 Mbps).
The system is extremely robust against disturbances such as noise and multipath fading.
Due to its primarily analog signal processing and the robustness of the chirp signal, nanoNET TRX has an extremely low power consumption per successfully transmitted bit. For battery-powered applications requiring a long life and high data rates, this IC offers the ideal solution. The data rate is selectable between 500 kbps, 1 Mbps, and 2 Mbps. Due to the unique chirp pulse, adjustment of the antenna is not critical, which significantly simplifies the installation and maintenance of the system (“pick and place”).
The nanoNET TRX transceiver includes a MAC controller with CSMA/CA and TDMA support, as well as Forward Error Correction (FEC), and 128 bit encryption.
Driver software, a Portable Protocol Stack (PPS), an Evaluation Kit, and a Development Kit are also available.

Main Features
* Operating worldwide in the 2.45 GHz ISM band
* Data rates: 2 Mbps and 1 Mbps
* Range: max 900 m free space, 60 m indoors (@ 8 dBm TX power, 1 Mbps)
* CSMA/CA and TDMA Support
* Modulation technique: Chirp Spread Spectrum
* Chirp bandwidth: 64 MHz effective
* Processing gain: 17 dB
* Carrier to Interference ratio: -3 dB to 0 dB (@ BER=10-3, C=-82 dBm, 1Mbps)
* Maximum RF output power: 8 dBm
* TX power adjustment in 19 steps from -27 dBm to 8 dBm
* Receiver sensitivity: -92 dBm (@ BER=10-3, 1Mbps)
* Supply voltage: 2.4 V to 3.6 V
* Current consumption: 35 mA (RX), 78 mA (TX, 8 dBm), 64 m (TX, 0 dBm)
* Standby current with active RTC is 1.5 μA
* Operating temperature range: -40° C to +85° C
* Integrated MAC controller with FEC and CRC
* SPI interface to external μc (up to 16 MHz SPI clock)
* 4 channel digital I/O
* Automatic address matching (48 bit)

Applications
* Active RFID
* Industrial Monitoring and Control
* Medical Applications
* Building Safety
* Meter and Sensor Reading
* Multimedia

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GENERAL DESCRIPTION
 The XR16M25501 (M2550) is a high performance dual universal asynchronous receiver and transmitter (UART) with 16 bytes TX and RX FIFOs.
The device operates from 1.62 to 3.63 volts and is pin-to-pin and software compatible to the ST16C2550, XR16L2550, and XR16V2550.
It supports Exar’s enhanced features of selectable FIFO trigger level, automatic hardware (RTS/CTS) and software flow control, and a complete modem interface.
Onboard registers provide the user with operational status and data error flags. An internal loopback capability allows system diagnostics.
Independent programmable baud rate generators are provided in each channel to select data rates up to 16 Mbps at 3.3 Volt with 4X sampling clock.
The M2550 is available in 48-pin TQFP and 32-pin QFN packages.

FEATURES
* 1.62 to 3.63 Volt Operation
* Pin-to-pin and software compatible to ST16C2550 in the 48-TQFP package
* Pin-to-pin and software compatible to XR16L2550 and XR16V2550
* Two independent UART channels
- Register set is 16550 compatible
- Data rate of up to 16 Mbps at 3.3 V
- Data rate of up to 12.5 Mbps at 2.5 V
- Data rate of up to 8 Mbps at 1.8V
- Fractional Baud Rate Generator
- Transmit and Receive FIFOs of 16 bytes
- Selectable TX and RX FIFO Trigger Levels
- Automatic Hardware (RTS/CTS) Flow Control
- Automatic Software (Xon/Xoff) Flow Control
- Wireless Infrared (IrDA 1.0) Encoder/Decoder
- Automatic sleep mode
- Full modem interface
* Device Identification and Revision
* Crystal oscillator (up to 24MHz) or external clock (up to 64MHz) input
* 48-TQFP and 32-QFN packages

APPLICATIONS
* Portable Appliances
* Telecommunication Network Routers
* Ethernet Network Routers
* Cellular Data Devices
* Factory Automation and Process Controls

XR16M2550IL32
XR16M2550IM48

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Description
* Highly Integrated Solution with Ranging
The nanoLOC TRX Transceiver is a highly integrated mixed signal chip utilizing Nanotron’s unique wireless communication technology CSS (Chirp Spread Spectrum).
With its unique ranging capability, nanoLOC can measure the link distance between two nodes. Thus, nanoLOC supports location-aware applications including Location Based Services (LBS), enhanced RFID, as well as asset tracking (2D/3D RTLS).
As ranging is performed during regular data communication, additional infrastructure, power, and/or bandwidth is not required.
* Improved Coexistence Performance
nanoLOC supports a freely adjustable center frequency with 3 non-overlapping frequency channels.
This provides support for multiple physically independent networks and improved coexistence performance with existing 2.4 GHz wireless technologies.
Data rates are selectable from 2 Mbps to 125 kbps.
Due to the chip’s unique chirp pulse, adjustment of the antenna is not critical.
This significantly simplifies the system’s installation and maintenance (“pick and place”).
A sophisticated MAC controller with CSMA/CA and TDMA support is included, as is Forward Error Correction (FEC) and 128 bit hardware encryption.
To minimize software and microcontroller requirements, nanoLOC also provides scrambling, automatic address matching, and packet retransmission.

Key Features
* Single chip 2.4 GHz RF Transceiver operating in the worldwide ISM Band
* Integrated MAC controller with FEC and CRC checking
* Automatic retransmission and acknowledgement, as well as automatic address matching
* Few external components required
* Link distance estimation with built-in ranging capability
- High precision ranging.. 2 m indoors / 1 m outdoors
* Low current consumption:
- Current consumption RX starts at .................33 mA
- Current consumption TX.................30 mA @ 0dBm
- Standby current with active RTC ...................1.2 μA
- Low supply voltage .................................2.3 – 2.7 V
* Modulation ...................Chirp Spread Spectrum (CSS)
* Media Access Techniques
- FDMA .........................3 non-overlapping channels
- CSMA/CA
- TDMA
* Programmable data rates..............2 Mbps to 125 kbps
* Clock available for external μC .................. 32.768 kHz
* Integrated fast SPI interface .......................... 32 Mbps
* Programmable output power............ -33 dBm – 0 dBm
* External power amplifier supported
* Receiver sensitivity ................................up to -97 dBm
* RSSI sensitivity ...............................................-95 dBm
* In-band C/I ..............3 dB @ 250 kbps & C = -80 dBm
* Industrial temperature range..............-40 °C to +85 °C

Applications
* Logistics: Asset tracking / Active RFID
* 2D / 3D Real Time Location Systems (RTLS)
* Industrial Monitoring and Control
* Security / Government
* Medical Applications

NLSG0501A

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Description
 The IS-5114 is a highly integrated solution for dual-mode digital still-image and video cameras. It combines a number of functions that are required in such devices, including the following:
* The device is based on an ARM946ES microprocessor whose function is to control the entire
system, to capture and play back audio, and to multiplex compressed video and audio into a
single bit stream that can be delivered to the main CPU.
Most computationally-intensive functions are implemented in hardware which can be programmed according to user specifications, thus allowing the ARM® processor to be free for other user-defined functions such as advanced image and multimedia processing.
The processor has 8 KB + 8 KB of internal instruction/data cache which helps it to operate efficiently and use minimal DDR SDRAM bandwidth.
* The device supports imager sizes of up to 16 megapixels.
It accepts both Bayer RGB and CCIR-656 interfaces, which cover all possible CCD and CMOS sensors.
It supports progressive as well as interlaced (up to 4 fields) imagers, including the special readout modes of progressive VGA CCD imagers.
The device also supports a programmable delay on the external imager clock so that the highest quality images can be captured.
* The device has a high-performance still-image and video image processing block that
performs all the necessary functions to convert the image/video data to a format that can be
compressed in either JPEG or MPEG formats, as well as deliver image data to the LCD controller for a live view.
This block performs gain control, color recovery, Gamma correction, image enhancement, image correction, scaling, rotation, and conversion to the YC format.
All those functions have been implemented in the hardware to achieve the required performance
at very low power consumption figures.
In addition, there is a hardware block that collects statistics on the imager for auto-exposure (AE) and auto-white balancing (AWB) algorithms.
Those AE/AWB algorithms are performed in the embedded ARM9 CPU to allow customization of the application.
The current architecture also has the appropriate interfaces and sufficient performance to support a strobe-type flash light, as well as dark frame subtraction for low-level light conditions.
* The device has numerous display capabilities.
It has an integrated video encoder (double sampling) and two 10-bit video DACs running at up to 27 MHz to support direct display to high-definition TVs and projectors.
The device also has a 24-bit RGB output to interface to flat-panel TVs (LCDs and Plasma) at different VESA rates up to XGA (1024 x 768) resolution.
It supports both square pixel and CCIR-type formats and can display in NTSC or PAL mode
with the same crystal.
It also has an integrated LCD controller which can interface directly to various LCDs.
It directly supports a variety of LCD panels from Epson, Casio, AU, and Toppoly without the need for external ICs.
Finally, it has a digital video output interface which can supply composite, 8-bit YC (CCIR-656), 16-bit YC, RGB 565, or component (Y/Pr/Pb) formats.
* The device has a high-performance image scaler that can perform up and down scaling at
floating point resolutions.
* For video applications, a hardware video codec is included that supports MPEG-4 Simple
Profile (encode and decode) and Advanced Simple Profile (encode only) communication at
up to 30 fps VGA resolution.
The hardware video engine is a pipelined architecture which is also flexible enough to support JPEG compression/decompression, H.263, MPEG-2 encode(I/P frames) at 30 fps VGA, and MPEG-1 encode/decode at 24 fps VGA (I frames only).
The video codec can also be used to record and play back video clips including those taken from other digital cameras and mobile phones.
All performance figures are for half duplex operation.
Full duplex is possible, but the performance has not been characterized.
* The device utilizes a unified memory architecture using the DDR-SDRAM to capture, process, and play back images and video as well as to store program code and variables.
It supports SDRAM configurations of up to 1 gigabit.
* The device supports all Flash cards, including Multimedia Card (MMC), Secure Digital (SD),
Memory Stick Pro, SSFDC/SmartMedia/NAND Flash, and CompactFlash.
The Flash card interfaces can support read/write operations at the maximum speeds specified by the Flash cards.
* The device has an ATA/IDE controller with UDMA capability to stream video directly to hard
drives or CompactFlash devices.
* A static memory controller is included that supports up to eight 16 MB devices such as Flash,
SRAM, or other memory-mapped peripherals.
Both 8-bit and16-bit data buses are supported, with data accesses of up to 32 bits.
The number of wait states, and setup, hold, and data float times are programmable on a per device (chip select) basis.
* A general-purpose 10-bit 96 kHz DAC is available.
It can be used to control camera components such as the iris, shutter motor, lens motor, flash bulb, or AGC gain. It can also be used to drive audio output.
* A general-purpose 10-bit, 96 kHz ADC is available.
This ADC has four input channels, which can be used for such things as battery level checking, photo detection, focus sensing, or audio capture.
* The I2S- and AC’97-compatible audio data interface allows the device to connect with an
external stereo ADC/DAC to capture or play back voice or audio.
The device can encode captured audio in various popular formats, and can package it in the same bit stream as the video or inside compressed JPEG pictures.
It can also play back stand-alone audio such as MP3 files, or audio embedded in MPEG bit streams.
* The USB 2.0 high-speed slave controller can be used to connect to a PC for efficient downloading of captured images to the PC.
The USB 2.0 full-speed host controller allows the device to connect directly to printers and other slave devices.
* An IEEE 1394 link layer interface allows the device to stream video (compressed or uncompressed) to other devices.
* Two USART interfaces are included for serial communication.
They support standard baud rates of up to 460.8 kbps or non-standard rates of up to 4.875 Mbps in asynchronous mode.
They support rates of up to 19.5 Mbps in synchronous mode.
* The Serial Peripheral Interface (SPI) is used to boot from an external EEPROM.
Once the boot code is loaded inside the program memory, the CPU can download its code from any peripheral supported by the device, including non-volatile storage media.
With four chip select pins, the SPI can also be used to control other external devices at speeds of up to 24 Mbps.
* Three 16-bit and three 32-bit general-purpose timers are included which can be used to
generate interrupts to the internal CPU.
The 16-bit timers can also generate waveforms on their associated pins via pulse-width modulation (PWM) or other techniques.
They can also monitor and count external events on these pins.
* A dedicated watchdog timer is available which can provide an interrupt, an event on an external pin, or a reset to the internal CPU in the event that software is not responding as
expected.
Write access to the watchdog is protected by control access keys to prevent corruption of the watchdog should an error condition occur.
* A real-time clock is provided to keep track of the time.
It operates on its own power supplies, so the clock can keep running with very low power consumption even if the rest of the chip is unpowered.
Two pins are provided to control system power switching.
* The device provides a keyboard interface that can monitor up to 25 buttons.
* The device provides up to 8 external interrupt pins, depending on the system configuration,
which can be handled by the interrupt controller as either edge or level sensitive.
* Up to 130 pins can also be configured as GPIOs, depending on the system application.
* During normal operation, the power consumption may be minimized by disabling the clock of
any internal module that is not in use.
In order to further reduce power consumption, the main CPU clock can be divided to run at a slower speed.
In order to minimize power consumption when the device is not in use, a “sleep mode” is available that halts the operation of all logic and shuts down the oscillators and PLLs.
Recovery from the sleep mode occurs via the WKP (“wake-up”) pin, at which time the device begins execution from its previous state.

Features
* Advanced Processor for Dual-mode Digital Still Cameras and Video Recorders
* Supports Personal Video Recording Applications
* ARM946E-S™ Core with Enhanced DSP Capability for A/V Processing and System Control Functions, 8 KBytes Each for Instruction/Data Cache, Runs up to 96 MHz
* Supports Progressive and Interlaced CCD Imagers (up to 4 Fields)
* Image Processing Functions for CCD/CMOS Imagers
* Image Scaling and Rotation Hardware
* Video Encoder with Two DACs and Line Drivers for Composite or S-Video NTSC/PAL TV
* Digital Video Outputs Include: Composite, 16/8-bit YC (CCIR-656), RGB 565, 24-bit RGB, Component (Y/Pr/Pb), VESA up to XGA Resolutions
* Direct Interface to Casio, Epson, AU, and Toppoly LCDs
* Encodes/Decodes Images and Video: Baseline JPEG, MPEG-1 at 24 fps VGA, MPEG-4 at 30 fps VGA (Performance Figures are for Half Duplex)
* DDR SDRAM Interface Supports from 128 Mbits to 1 Gbit
* Unified Memory Architecture (Entire Program and Data Stored in DDR SDRAM)
* Support for All Flash Card Interfaces (MMC/SD, Memory Stick Pro™, SSFDC/SmartMedia, CompactFlash®)
* ATA/IDE Controller
* Static Memory Controller (Flash/SRAM) Supports up to Eight 16 MB Devices
* One DAC for Camera Control Functions and Audio Output
* Four ADC Channels for Monitoring Camera Analog Inputs (Audio, Switches, etc.)
* Audio Data Interface for Connection to External Stereo ADC/DAC
* USB 2.0 High-speed Slave and Full-speed Host Controllers for PC Camera and Printing Applications
* IEEE 1394 Link Layer Interface
* Two USART Interfaces and a Serial Peripheral Interface (SPI) for Loading Boot Code and Controlling Camera Components
* Six General-purpose Timers for Waveform Generation (PWM, etc.) and Event Monitoring
* Programmable Watchdog Timer and Real-time Clock
* Keyboard Interface Supports up to 25 Buttons
* Up to 8 External Interrupts and up to 130 Pins Configurable as General-purpose I/Os
* 280-ball BGA Package, 1.8V Core, and 1.8 to 3.3V I/O Operation

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Description
 The TM54S816T is organized as 4-bank x 2097152-word x 16-bit(8Mx16), fabricated with high performance CMOS technology.
Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.

Features
* Package: 400-mil 54-pin TSOP(II)
* JEDEC PC133/PC100 compatible
* Single 3.3V Power Supply
* LVTTL Signal Compatible
* Programmable
- CAS Latency (3 or 2 clocks)
- Burst Length (1,2,4, 8 & full page)
- Burst type (Sequential & Interleave)
* Burst read/write and burst read/single write operations capability
* Byte control(DQML and DQMU)
* Auto and Self Refresh
* 64ms refresh period (4K Refresh)
* 12-Row x 9-Column organization
* 4-Bank operation controlled by BA1,BA0
* Pin36 and 40 are “No Connected”
* Fully synchronous operation referenced to clock rising edge

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Description
 The GAL16V8, at 3.5 ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E2) floating gate technology to provide the highest speed
performance available in the PLD market.
High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.
An important subset of the many architecture configurations possible with the GAL16V8 are the PAL architectures listed in the table of the macrocell description section.
GAL16V8 devices are capable of emulating any of these PAL architectures with full function/fuse map/parametric compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture.
As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products.
In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
• HIGH PERFORMANCE E2CMOS® TECHNOLOGY
- 3.5 ns Maximum Propagation Delay
- Fmax = 250 MHz
- 3.0 ns Maximum from Clock Input to Data Output
- UltraMOS® Advanced CMOS Technology
• 50% to 75% REDUCTION IN POWER FROM BIPOLAR
- 75mA Typ Icc on Low Power Device
- 45mA Typ Icc on Quarter Power Device
• ACTIVE PULL-UPS ON ALL PINS
• E2 CELL TECHNOLOGY
- Reconfigurable Logic
- Reprogrammable Cells
- 100% Tested/100% Yields
- High Speed Electrical Erasure (<100ms)
- 20 Year Data Retention
• EIGHT OUTPUT LOGIC MACROCELLS
- Maximum Flexibility for Complex Logic Designs
- Programmable Output Polarity
- Also Emulates 20-pin PAL® Devices with Full Function/Fuse Map/Parametric Compatibility
• PRELOAD AND POWER-ON RESET OF ALL REGISTERS
- 100% Functional Testability
• APPLICATIONS INCLUDE:
- DMA Control
- State Machine Control
- High Speed Graphics Processing
- Standard Logic Speed Upgrade
• ELECTRONIC SIGNATURE FOR IDENTIFICATION
• LEAD-FREE PACKAGE OPTIONS

GAL16V8D-25LJ
GAL16V8D-25LS
GAL16V8D-15QPN

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