Description
Xilinx introduces the QPro™ XQ18V04 Military Grade 4Mbit in-system programmable configuration Flash PROM. The XQ18V04 is a 3.3V rewritable PROM that provides a reliable non-volatile method for storing large Xilinx FPGA configuration bitstreams used in systems that
require operation over the full military temperature range.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in SelectMAP mode (Slave), an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data
is available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are
interconnected. The XQ18V04 is compatible and can be cascaded with other configuration PROMs such as the XQR1701L and XQR17V16 one-time programmable configuration
PROMs.

Features
*Operating Temperature Range: –55° C to +125°C
*Low-power advanced CMOS FLASH process memory cells immune to static single event upset
*In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
*IEEE Std 1149.1 boundary-scan (JTAG) support
*Cascadable for storing longer or multiple bitstreams
*Dual configuration modes
- Serial Slow/Fast configuration (up to 20 MHz)
- Parallel (up to 160 Mbps at 20 MHz)
*5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals
*3.3V or 2.5V output capability
*Available in plastic VQ44 packaging only
*Design support using the Xilinx Alliance Series™ and Xilinx Foundation Series™ software packages
*JTAG command initiation of standard FPGA configuration

XQV300, XQV600, XQV1000

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General Description
The AM93LC66 is the 4096-bit non-volatile serial EEPROM.
It is manufactured by using ATC's advanced CMOS EEPROM technology.
The AM93LC66 provides efficient non-volatile read/write memory arranged as 256 words of 16 bits each when the ORG Pin is connected to VCC and 512 words of 8 bits each when it is tied to ground.
The instruction set includes read, write, and write enable/disable functions.
The data out pin (DO) indicates the status of the device during the self-timed non-volatile programming cycle.
The self-timed write cycle includes an automatic erase-before-write capability.
Only when the chip is in the WRITE ENABLE state and proper VCC operation range is the WRITE instruction accepted and thus to protect against inadvertent writes.
 Data is written in 16 bits per write instruction into the selected register.
 If Chip Select (CS) is brought HIGH after initiation of the write cycle, the Data Output (DO) pin will indicate the READY/BUSY status of the chip.
The AM93LC66 is available in space-saving 8-lead PDIP, 8-lead SOP and rotated 8-lead SOP package.

Features
*State-of-the-art architecture
-Non-volatile data storage
-Standard voltage and low voltage operation
Vcc: 2.7V ~ 5.5V
-Full TTL compatible inputs and outputs
-Auto increment read for efficient data dump
*Hardware and software write protection
-Defaults to write-disabled state at power up
-Software instructions for write-enable/disable
-VCC level verification before self-timed
programming cycle
*Advanced low voltage CMOS EEPROM
technology
*Versatile, easy-to-use interface
-Self-timed programming cycle
-Automatic erase-before-write
-Programming status indicator
-Word and chip erasable
-Stop SK anytime for power savings
*Durability and reliability
-40 years data retention
-Minimum of 1M write cycles per word
-Unlimited read cycles
-ESD protection

AM93LC66
AM93LC66I
AM93LC66V

TAG PROM

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Description
 Xilinx introduces the XC18V00 series of in-system programmable configuration PROMs.
Devices in this 3.3V family include a 4-megabit, a 2-megabit, a 1-megabit, and a 512-kilobit PROM that provide an easy-touse, cost-effective method for reprogramming and storing Xilinx FPGA configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM.
A short access time after CE and OE are enabled, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin.
New data is available a short access time after each rising clock edge.
The FPGA generates the appropriate number of clock pulses to complete the configuration.
When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock.
When the FPGA is in Master SelectMAP mode, the FPGA generates a configuration clock that drives the PROM.
When the FPGA is in Slave Parallel or Slave SelectMAP mode, an external oscillator generates the configuration clock that drives the PROM and the FPGA.
After CE and OE are enabled, data is available on the PROM’s DATA (D0-D7) pins.
New data is available a short access time after each rising clock edge.
The data is clocked into the FPGA on the following rising edge of the CCLK.
A free-running oscillator can be used in the Slave Parallel or Slave SelecMAP modes.
Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device.
The clock inputs and the DATA outputs of all PROMs in this chain are interconnected.
All devices are compatible and can be cascaded with other members of the family or with the XC17V00 one-time programmable serial PROM family.

Features
* In-System Programmable 3.3V PROMs for Configuration of Xilinx FPGAs
- Endurance of 20,000 Program/Erase Cycles
- Program/Erase Over Full Industrial Voltage and Temperature Range (–40°C to +85°C)
* IEEE Std 1149.1 Boundary-Scan (JTAG) Support
* JTAG Command Initiation of Standard FPGA Configuration
* Simple Interface to the FPGA
* Cascadable for Storing Longer or Multiple Bitstreams
* Low-Power Advanced CMOS FLASH Process
* Dual Configuration Modes
- Serial Slow/Fast Configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
* 5V-Tolerant I/O Pins Accept 5V, 3.3V and 2.5V Signals
* 3.3V or 2.5V Output Capability
* Design Support Using the Xilinx ISE™ Foundation™ Software Packages
* Available in PC20, SO20, PC44, and VQ44 Packages
* Lead-Free (Pb-Free) Packaging

XC18V04
XC18V02
XC18V01
XC18V512

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