Genaral Descroption
The ISL6323 dual PWM controller delivers high efficiency and tight regulation from two synchronous buck DC/DC converters. The ISL6323 supports hybrid power control of AMD processors which operate from either a 6-bit parallel VID interface (PVI) or a serial VID interface (SVI). The dual output ISL6323 features a multi-phase controller to support uniplane VDD core voltage and a single phase controller to power the Northbridge (VDDNB) in SVI mode. Only the multi-phase controller is active in PVI mode to support uniplane VDD only processors.
A precision uniplane core voltage regulation system is provided by a two-to-four-phase PWM voltage regulator (VR) controller. The integration of two power MOSFET drivers, adding flexibility in layout, reduce the number of external components in the multi-phase section. A single phase PWM controller with integrated driver provides a second precision voltage regulation system for the North Bridge portion of the processor. This monolithic, dual controller with integrated driver solution provides a cost and space saving power management solution.
For applications which benefit from load line programming to reduce bulk output capacitors, the ISL6323 features output voltage droop. The multi-phase portion also includes advanced control loop features for optimal transient response to load application and removal. One of these features is highly accurate, fully differential, continuous DCR current sensing for load line programming and channel current balance. Dual edge modulation is another unique feature,
allowing for quicker initial response to high di/dt load transients.

*Processor Core Voltage Via Integrated Multi-Phase Power Conversion
*Configuration Flexibility
- 2-Phase Operation with Internal Drivers
- 3- or 4-Phase Operation with External PWM Drivers
*Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
*Parallel VID Interface Inputs
- 6-bit VID input
- 0.775V to 1.55V in 25mV Steps
- 0.375V to 0.7625V in 12.5mV Steps
*Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
- Adjustable Reference-Voltage Offset
*Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
*Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
*Variable Gate Drive Bias: 5V to 12V
*Overcurrent Protection
*Multi-tiered Overvoltage Protection
*Selectable Switching Frequency up to 1MHz
*Simultaneous Digital Soft-Start of Both Outputs
*Processor NorthBridge Voltage Via Single Phase Power Conversion
*Precision Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.5% System Accuracy Over-Temperature
*Serial VID Interface Inputs
- Two Wire, Clock and Data, Bus
- Conforms to AMD SVI Specifications
*Overcurrent Protection
*Continuous DCR Current Sensing
*Variable Gate Drive Bias: 5V to 12V
*Simultaneous Digital Soft-Start of Both Outputs
*Selectable Switching Frequency up to 1MHz
*Pb-Free (RoHS Compliant)


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ㅁ Features
· C672x: 32-/64-Bit 300-MHz Floating-Point DSPs
· Upgrades to C67x+ CPU From C67x™ DSP
– 2X CPU Registers [64 General-Purpose]
– New Audio-Specific Instructions
– Compatible With the C67x CPU
· Enhanced Memory System
– 256K-Byte Unified Program/Data RAM
– 384K-Byte Unified Program/Data ROM
– Single-Cycle Data Access From CPU
– Large Program Cache (32K Byte) Supports RAM, ROM, and External Memory
· External Memory Interface (EMIF) Supports
– 133-MHz SDRAM (16- or 32-Bit)
– Asynchronous NOR Flash, SRAM (8-,16-, or 32-Bit)
– NAND Flash (8- or 16-Bit)
· Enhanced I/O System
– High-Performance Crossbar Switch
– Dedicated McASP DMA Bus
– Deterministic I/O Performance
· dMAX (Dual Data Movement Accelerator)
– 16 Independent Channels
– Concurrent Processing of Two Transfer Requests
– 1-, 2-, and 3-Dimensional Memory-to-Memory and Memory-to-Peripheral Data Transfers
– Circular Addressing Where the Size of a Circular Buffer (FIFO) is not Limited to 2n
– Table-Based Multi-Tap Delay Read and Write Transfers From/To a Circular Buffer
· Three Multichannel Audio Serial Ports
– Transmit/Receive Clocks up to 50 MHz
– Six Clock Zones and 16 Serial Data Pins
– Supports TDM, I2S, and Similar Formats
– DIT-Capable (McASP2)
· Universal Host-Port Interface (UHPI)
– 32-Bit-Wide Data Bus for High Bandwidth
– Muxed and Non-Muxed Address and Data
· Two 10-MHz SPI Ports With 3-, 4-, and 5-Pin Options
· Two Inter-Integrated Circuit (I2C) Ports
· Real-Time Interrupt Counter/Watchdog
· Oscillator- and Software-Controlled PLL
· Applications:
– Professional Audio
· Mixers
· Effects Boxes
· Audio Synthesis
· Instrument/Amp Modeling
· Audio Conferencing
· Audio Broadcast
· Audio Encoder
– Emerging Audio Applications
– Biometrics
– Medical
– Industrial
· Commercial or Extended Temperature
· 144-Pin, 0.5-mm, PowerPAD™ Thin Quad Flatpack (TQFP) [RFP Suffix]
· 256-Terminal, 1.0-mm, 16x16 Array Plastic Ball Grid Array (PBGA) [GDH and ZDH Suffixes]

TMS320C6727B TMS320C6726B TMS320C6722B TMS320C6720 TMS320C6720BRFP200 TMS320C6722BRFP200 TMS320C6722BRFP250 TMS320C6726BRFP266 TMS320C6727BGDH275 TMS320C6727BGDH300 TMS320C6727BZDH275 TMS320C6727BZDH300

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Available in TDA8360, TDA8361 and TDA8362
· Vision IF amplifier with high sensitivity and good differential gain and phase
· Multistandard FM sound demodulator (4.5 MHz to 6.5 MHz)
· Integrated chrominance trap and bandpass filters (automatically calibrated)
· Integrated luminance delay line
· RGB control circuit with linear RGB inputs and fast blanking
· Horizontal synchronization with two control loops and alignment-free horizontal oscillator without external components
· Vertical count-down circuit (50/60 Hz) and vertical preamplifier
· Low dissipation (700 mW)
· Small amount of peripheral components compared with competition ICs
· Only one adjustment (vision IF demodulator)
· The supply voltage for the ICs is 8 V. They are mounted in a shrink DIL envelope with 52 pins and are pin compatible.

Additional features
· Alignment-free PAL colour decoder for all PAL standards, including PAL-N and PAL-M.
· PAL/NTSC colour decoder with automatic search system
· Source selection for external audio/video (A/V) inputs (separate Y/C signals can also be applied).
· Multistandard vision IF circuit (positive and negative modulation)
· PAL/NTSC colour decoder with automatic search system · Source selection for external A/V inputs (separate Y/C signals can also be applied)
· Easy interfacing with the TDA8395 (SECAM decoder) for multistandard applications.

The TDA8360, TDA8361 and TDA8362 are single-chip TV processors which contain nearly all small signal functions that are required for a colour television receiver. For a complete receiver the following circuits need to be added: a base-band delay line (TDA4661), a tuner and output stages for audio, video and horizontal and vertical deflection. Because of the different functional contents of the ICs the set maker can make the optimum choice depending on the requirements for the receiver. The TDA8360 is intended for simple PAL receivers (all PAL standards, including PAL-N and PAL-M are possible). The TDA8361 contains a PAL/NTSC decoder and has an A/V switch. For real multistandard applications the TDA8362 is available. In addition to the extra functions which are available in the TDA8361, the TDA8362 can handle signals with positive modulation and it supplies the signals which are required for the SECAM decoder TDA8395.

TDA8360 TDA8361 TDA8362

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ㅁHighest-Performance Fixed-Point Digital Signal Processors (DSPs)
− 2-, 1.67-, 1.39-ns Instruction Cycle Time
− 600-MHz Clock Rate
− Eight 32-Bit Instructions/Cycle
− Twenty-Eight Operations/Cycle
− 4800 MIPS
− Fully Software-Compatible With C62x
− C6414/15/16 Devices Pin-Compatible
ㅁVelociTI.2 Extensions to VelociTI Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x DSP Core
− Eight Highly Independent Functional Units With VelociTI.2 Extensions:
− Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
− Two Multipliers Support Four 16 x 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight
8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
− Non-Aligned Load-Store Architecture
− 64 32-Bit General-Purpose Registers
− Instruction Packing Reduces Code Size
− All Instructions Conditional
ㅁInstruction Set Features
− Byte-Addressable (8-/16-/32-/64-Bit Data)
− 8-Bit Overflow Protection
− Bit-Field Extract, Set, Clear
− Normalization, Saturation, Bit-Counting
− VelociTI.2 Increased Orthogonality
ㅁViterbi Decoder Coprocessor (VCP) [C6416]
− Supports Over 500 7.95-Kbps AMR
− Programmable Code Parameters
ㅁTurbo Decoder Coprocessor (TCP) [C6416]
− Supports up to Six 2-Mbps 3GPP (6 Iterations)
− Programmable Turbo Code and Decoding Parameters
ㅁL1/L2 Memory Architecture
− 128K-Bit (16K-Byte) L1P Program Cache (Direct Mapped)
− 128K-Bit (16K-Byte) L1D Data Cache (2-Way Set-Associative)
− 8M-Bit (1024K-Byte) L2 Unified Mapped RAM/Cache (Flexible Allocation)
ㅁTwo External Memory Interfaces (EMIFs)
− One 64-Bit (EMIFA), One 16-Bit (EMIFB)
− Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO)
− 1280M-Byte Total Addressable External Memory Space
ㅁEnhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
ㅁHost-Port Interface (HPI)
− User-Configurable Bus Width (32-/16-Bit)
ㅁ32-Bit/33-MHz, 3.3-V PCI Master/Slave Interface Conforms to PCI Specification 2.2 [C6415/C6416 ]
− Three PCI Bus Address Registers: Prefetchable Memory Non-Prefetchable Memory I/O
− Four-Wire Serial EEPROM Interface
− PCI Interrupt Request Under DSP Program Control
− DSP Interrupt Via PCI I/O Cycle
ㅁThree Multichannel Buffered Serial Ports
− Direct Interface to T1/E1, MVIP, SCSA Framers
− Up to 256 Channels Each
− ST-Bus-Switching-, AC97-Compatible
− Serial Peripheral Interface (SPI) Compatible (Motorola)
ㅁThree 32-Bit General-Purpose Timers
ㅁUniversal Test and Operations PHY Interface for ATM (UTOPIA) [C6415/C6416]
− UTOPIA Level 2 Slave ATM Controller
− 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
− User-Defined Cell Format up to 64 Bytes
ㅁSixteen General-Purpose I/O (GPIO) Pins
ㅁFlexible PLL Clock Generator
ㅁIEEE-1149.1 (JTAG†) Boundary-Scan-Compatible
ㅁ570-Pin Grid Array (PGA) Package (GAD Suffix)
ㅁ0.13-μm/6-Level Cu Metal Process (CMOS)
ㅁ3.3-V I/Os, 1.4-V Internal

SMJ320C6414DGADW60 SM320C6414DGADW60 SMJ320C6415DGADW60 SM320C6415DGADW60 SMJ320C6416DGADW60 SM320C6416DGADW60†

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