The ADF4150 allows implementation of fractional-N or integer-N phase-locked loop (PLL) frequency synthesizers if used with an external Voltage Controlled Oscillator (VCO), loop filter and external reference frequency.
The ADF4150 is for use with external VCO parts and is software compatible with the ADF4350. The VCO frequency can be divided-by 1/2/4/8 or 16 to allow the user to generate RF output frequencies as low as 31.25 MHz. For applications that require isolation the RF output stage can be muted. The mute function is both pin and software controllable.
Control of all the on-chip registers is through a simple 3-wire interface. The device operates with a power supply ranging from 3.0 V to 3.6 V and can be powered down when not in use.
The ADF4150 is available in a 4mm x 4mm package.

*Fractional-N synthesizer and integer-N synthesizer
*Programmable divide-by-1/2/4/8 or 16 output
*3.0 V to 3.6 V power supply
*1.8 V logic compatibility
*Separate charge pump supply (VP) allows extended tuning
*voltage in 3 V systems
*Programmable dual-modulus prescaler of 4/5 or 8/9
*Programmable output power level
*RF output mute function
*3-wire serial interface
*Analog and digital lock detect
*Switched bandwidth fast-lock mode
*Cycle slip reduction

*Wireless infrastructure (WCDMA, TD-SCDMA, WiMax, GSM, PCS, DCS, DECT)
*Test equipment
*Wireless LANs, CATV equipment
*Clock Generation


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The SP5848 is a dual PLL frequency synthesizer controlled by a 3-wire bus optimised for application in double conversion tuners.
Each synthesiser loop within the SP5848 is independently addressable and contains an RF programmable divider, phase/frequency detector and charge pump/loop amplifier section; a common reference frequency oscillator and divider chain is provided, whose ratios for each loop are independently programmable.
Both synthesisers are optimised for low phase noise performance and in addition synthesiser 2 is capable of operation with a low comparison frequency.

*Dual independent PLL frequency synthesisers in a single package, optimised for double conversion cable tuners, offering improved application
*2.2GHz up-synthesiser optimised for low phase noise up to comparison frequencies of 4MHz
*1.3GHz down-synthesiser optimised for low phase noise AND small step size
*Common reference oscillator and divider with independently selectable ratios for each synthesiser
*10:1 programmable charge pump current ratio in up synthesiser
*3-Wire bus programmable, each synthesiser indepently addressable
*Low power consumption, typ 100mW at 5V
*ESD protection, (Normal ESD handling procedures should be observed)

*TV, VCR, and cable tuning systems

SP5848/KG/QP1S, SP5848/KG/QP1T
TAG dual, PLL

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The ZL30402 is a Network Element Phase-Locked Loop designed to synchronize SDH and SONET systems. In addition, it generates multiple clocks for legacy PDH equipment and provides timing for ST-BUS and GCI backplanes.
The ZL30402 operates in NORMAL (LOCKED), HOLDOVER and FREE-RUN modes to ensure that in the presence of jitter, wander and interruptions to the reference signals, the generated clocks meet international standards. The filtering characteristics of the PLL are hardware or software selectable and they do not require any external adjustable components. The ZL30402 uses an external 20 MHz Master Clock Oscillator to provide a stable timing source for the HOLDOVER operation.
The ZL30402 operates from a single 3.3 V power supply and offers a 5 V tolerant microprocessor interface.

*Meets requirements of GR-253 for SONET stratum 3 and SONET Minimum Clocks (SMC)
*Meets requirements of GR-1244 for stratum 3
*Meets requirements of G.813 Option 1 and 2 for SDH Equipment Clocks (SEC)
*Generates clocks for ST-BUS, DS1, DS2, DS3, OC-3, E1, E2, E3, STM-1 and 19.44 MHz
*Holdover accuracy to 1x10 -12 meets GR-1244 Stratum 3E and ITU-T G.812 requirements
*Continuously monitors Primary and Secondary reference clocks
*Provides “hit-less” reference switching
*Compensates for Master Clock Oscillator accuracy
*Detects frequency of both reference clocks and synchronizes to any combination of 8 kHz,
1.544 MHz, 2.048 MHz and 19.44 MHz reference frequencies.
*Allows Hardware or Microprocessor control
*Pin compatible with MT90401 device.

*Synchronization for SDH and SONET Network Elements
*Clock generation for ST-BUS and GCI backplanes

ZL30402/QCC, ZL30402QCC1

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The ICS841S01 is a PLL-based clock generator specifically designed for PCI_Express™Clock
Generation applications. This device generates a 100MHz HCSL clock. The device offers a HCSL (Host Clock Signal Level) clock output from a clock input reference of 25MHz. The input reference may be derived from an external source or by the addition of a 25MHz crystal to the on-chip crystal oscillator. An external reference may be applied to the XTAL_IN pin with the XTAL_OUT pin left floating.
The device offers spread spectrum clock output for reduced EMI applications. An I2C bus interface is used to enable or disable spread spectrum operation as well as select either a down spread value of -0.35% or -0.5%.
The ICS841S01 is available in both standard and lead-free 16-Lead TSSOP packages.

*One 0.7V current mode differential HCSL output pair
*Crystal oscillator interface, 25MHz
*Output frequency: 100MHz
*RMS period jitter: 3ps (maximum)
*Cycle-to-cyle jitter: 35ps (maximum)
*I2C support with readback capabilities up to 400kHz
*Spread Spectrum for electromagnetic interference (EMI) reduction
*3.3V operating supply mode
*0°C to 70°C ambient operating temperature
*Available in both standard (RoHS 5) and lead-free (RoHS 6) packages


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The PE3282A is a dual fractional-N phase-locked loop integrated circuit designed for frequency synthesis and fabricated on Peregrine’s patented UTSi® CMOS process.
Each PLL includes a prescaler, phase detector, charge pump and on-board fractional spur compensation.
The 32/33 RF prescaler (PLL1) operates up to 1.1 GHz and the 16/17 IF prescaler (PLL2) operates up to 510 MHz.
The PE3282A provides fractional-N division with power-of-two denominator values up to 32. This allows comparison frequencies up to 32 times the channel spacing, providing a lower phase-noise floor than integer PLLs.

* Modulo-32 fractional-N main counters
* On-board fractional spur compensation: no tuning required, stable over temperature
* Improved phase noise compared to integer-N architectures
* Low power—8.5 mA at 3 V
* Integrated 1.1 GHz ÷ 32/33 prescaler
* Integrated 510 MHz ÷ 16/17 prescaler

* Cellular handsets
* Cellular base stations
* Spread-spectrum radio
* Cordless phones
* Pagers

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M61101FP is a semiconductor integrated circuit consisting of VIF/SIF signal processing such as mobile phones, notebook PCs with low voltage and low consumption.

• PLL split-carrier VIF/ SIF signal processing system compliant with NTSC

• Recommended supply voltage: 3.3V
• Adjustment free
• Coil-less VCO
• Built-in SIF trap and SIF band-pass filter
• Split-carrier system enables VIF and SIF signal processing independently.
• FM radio reception capability
• Package: QFN with 28pin

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General Description
The CD4046BC micropower phase-locked loop (PLL) consists of a low power, linear, voltage-controlled oscillator (VCO), a source follower, a zener diode, and two phase comparators. The two phase comparators have a common signal input and a common comparator input. The signal input can be directly coupled for a large voltage signal, or capacitively coupled to the self-biasing amplifier at the signal input for a small voltage signal. Phase comparator I, an exclusive OR gate, provides a digital error signal (phase comp. I Out) and maintains 90° phase shifts at the VCO center frequency. Between signal input and comparator input (both at 50% duty cycle), it may lock onto the signal input frequencies that are close to harmonics of the VCO center frequency. Phase comparator II is an edge-controlled digital memory network. It provides a digital error signal (phase comp. II Out) and lock-in signal (phase pulses) to indicate a locked condition and maintains a 0° phase shift between signal input and comparator input.
The linear voltage-controlled oscillator (VCO) produces an output signal (VCO Out) whose frequency is determined by the voltage at the VCOIN input, and the capacitor and resistors
connected to pin C1A, C1B, R1 and R2. The source follower output of the VCOIN (demodulator Out) is used with an external resistor of 10 kΩ or more. The INHIBIT input, when high, disables the VCO and source follower to minimize standby power consumption. The zener diode is provided for power supply regulation, if necessary.

- Wide supply voltage range: 3.0V to 18V
- Low dynamic power consumption: 70 µW (typ.)
at fo = 10 kHz, VDD = 5V
- VCO frequency: 1.3 MHz (typ.) at VDD = 10V
- Low frequency drift: 0.06%/°C at VDD = 10V with
- High VCO linearity: 1% (typ.)


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