DESCRIPTION
The GAL22LV10D, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL22LV10C can interface with both 3.3V and 5V signal levels. The GAL22LV10 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and
functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

FEATURES
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-4 ns Maximum Propagation Delay
-Fmax = 250 MHz
-3 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
*3.3V LOW VOLTAGE 22V10 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
-I/O Interfaces with Standard 5V TTL Devices (GAL22LV10C)
*ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*TEN OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION 22LV10D

GAL22LV10D-4LJ, GAL22LV10D-5LJ, GAL22LV10C-7LJ, GAL22LV10C-10LJ

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Description
The GAL20LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL20LV8D is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. An important subset of the many architecture configurations possible with the GAL20LV8D are the PAL architectures listed in the table of the macrocell description section. GAL20LV8D devices are capable of emulating any of these PAL architectures with full function/fuse map compatibility.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.5 ns Maximum Propagation Delay
-Fmax = 250 MHz
-2.5 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
-TTL-Compatible Balanced 8mA Output Drive
*3.3V LOW VOLTAGE 20V8 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
*ACTIVE PULL-UPS ON ALL PINS
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL20LV8D-3LJ, GAL20LV8D-5LJ, GAL20LV8D-7LJ

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Description
The GAL20V8Z and GAL20V8ZD, at 100 μA standby current and 12ns propagation delay provides the highest speed and lowest power combination PLD available in the market. The GAL20V8Z/ZD is manufactured using Lattice Semiconductor's advanced zero power E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology.
The GAL20V8Z uses Input Transition Detection (ITD) to put the device in standby mode and is capable of emulating the full functionality of the standard GAL20V8. The GAL20V8ZD utilizes a dedicated power-down pin (DPP) to put the device in standby mode. It has 19 inputs available to the AND array.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
*ZERO POWER E2CMOS TECHNOLOGY
-100μA Standby Current
-Input Transition Detection on GAL20V8Z
-Dedicated Power-down Pin on GAL20V8ZD
-Input and Output Latching During Power Down
*HIGH PERFORMANCE E2CMOS TECHNOLOGY
-12 ns Maximum Propagation Delay
-Fmax = 83.3 MHz
-8 ns Maximum from Clock Input to Data Output
-TTL Compatible 16 mA Output Drive
-UltraMOS® Advanced CMOS Technology
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
-Architecturally Similar to Standard GAL20V8
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Battery Powered Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
*ELECTRONIC SIGNATURE FOR IDENTIFICATION

GAL20V8ZD, GAL20V8Z-12QP, GAL20V8Z-12QJ, GAL20V8ZD-12QP
TAG E2CMOS, PLD, Power

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Description
The XCR22V10 is the first SPLD to combine high performance with low power, without the need for "turbo bits" or other power down schemes. To achieve this, Xilinx has used their FZP design technique, which replaces conventional sense amplifier methods for implementing product terms (a technique that has been used in PLDs since the bipolar era) with a cascaded chain of pure CMOS gates. This results in the combination of low power and high speed that has previously been unattainable in the PLD arena. For 3V operation, Xilinx offers the XCR22LV10 that offers high speed and low power in a 3V implementation.
The XCR22V10 uses the familiar AND/OR logic array structure, which allows direct implementation of sum-of-products equations. This device has a programmable AND array which drives a fixed OR array. The OR sum of products feeds an "Output Macro Cell" (OMC), which can be individually configured as a dedicated input, a combinatorial output, or a registered output with internal feedback.

Features
*Industry's first TotalCMOS™ SPLD - both CMOS design and process technologies
*Fast Zero Power (FZP™) design technique provides ultra-low power and high speed
-Static current of less than 75 μA
-Dynamic current substantially below that of competing devices
-Pin-to-pin delay of only 7.5 ns
*True Zero Power device with no turbo bits or power down schemes
*Function/JEDEC map compatible with Bipolar, UVCMOS, EECMOS 22V10s
*Multiple packaging options featuring PCB-friendly flow-through pinouts (SOL and TSSOP)
-24-pin TSOIC–uses 93% less in-system space than a 28-pin PLCC
-24-pin SOIC
-28-pin PLCC with standard JEDEC pinout
*Available in commercial and industrial operating ranges
*Advanced 0.5μ E2CMOS process
*1000 erase/program cycles guaranteed
*20 years data retention guaranteed
*Varied product term distribution with up to 16 product terms per output for complex functions
*Programmable output polarity
*Synchronous preset/asynchronous reset capability
*Security bit prevents unauthorized access
*Electronic signature for identification
*Design entry and verification using industry standard CAE tools
*Reprogrammable using industry standard device programmers

XCR22V10-10SO24, XCR22V10-7SO24, XCR22V10-10VO24C, XCR22V10-7VO24C

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Description
The GAL16LV8D, at 3.5 ns maximum propagation delay time, provides the highest speed performance available in the PLD market. The GAL16LV8C can interface with both 3.3V and 5V signal levels. The GAL16LV8 is manufactured using Lattice Semiconductor's advanced 3.3V E2CMOS process, which combines CMOS with Electrically Erasable (E2) floating gate technology. High speed erase times (<100ms) allow the devices to be reprogrammed quickly and efficiently.
The 3.3V GAL16LV8 uses the same industry standard 16V8 architecture as its 5V counterpart and supports all architectural features such as combinatorial or registered macrocell operations.
Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. As a result, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.

Features
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-3.5 ns Maximum Propagation Delay
-Fmax = 250 MHz
-2.5 ns Maximum from Clock Input to Data Output
-UltraMOS® Advanced CMOS Technology
*3.3V LOW VOLTAGE 16V8 ARCHITECTURE
-JEDEC-Compatible 3.3V Interface Standard
-5V Compatible Inputs
-I/O Interfaces with Standard 5V TTL Devices (GAL16LV8C)
*ACTIVE PULL-UPS ON ALL PINS (GAL16LV8D Only)
*E2 CELL TECHNOLOGY
-Reconfigurable Logic
-Reprogrammable Cells
-100% Tested/100% Yields
-High Speed Electrical Erasure (<100ms)
-20 Year Data Retention
*EIGHT OUTPUT LOGIC MACROCELLS
-Maximum Flexibility for Complex Logic Designs
-Programmable Output Polarity
*PRELOAD AND POWER-ON RESET OF ALL REGISTERS
-100% Functional Testability
*APPLICATIONS INCLUDE:
-Glue Logic for 3.3V Systems
-DMA Control
-State Machine Control
-High Speed Graphics Processing
-Standard Logic Speed Upgrade
*ELECTRONIC SIGNATURE FOR IDENTIFICATION
*LEAD-FREE PACKAGE OPTIONS

GAL16LV8D-3LJ, GAL16LV8D-5LJ, GAL16LV8C-7LJ, GAL16LV8C-10LJ

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Description
The ispLSI 1048E is a High Density Programmable Logic Device containing 288 Registers, 96 Universal I/O pins, 12 Dedicated Input pins, four Dedicated Clock Input pins, two dedicated Global OE input pins, and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1048E offers 5V non-volatile in-system programmability of the logic, as well as the interconnect to provide truly reconfigurable systems. A functional superset of the ispLSI 1048 architecture, the ispLSI 1048E device adds two new global output enable pins and two additional dedicated inputs.
The basic unit of logic on the ispLSI 1048E device is the Generic Logic Block (GLB). The GLBs are labeled A0, A1…F7 (see Figure 1). There are a total of 48 GLBs in the ispLSI 1048E device. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.

Features
*HIGH DENSITY PROGRAMMABLE LOGIC
-8,000 PLD Gates
-96 I/O Pins, Twelve Dedicated Inputs
-288 Registers
-High-Speed Global Interconnects
-Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
-Small Logic Block Size for Random Logic
-Functionally and Pin-out Compatible to ispLSI 1048C
*HIGH PERFORMANCE E2CMOS® TECHNOLOGY
-fmax = 125 MHz Maximum Operating Frequency
-tpd = 7.5 ns Propagation Delay
-TTL Compatible Inputs and Outputs
-Electrically Eraseable and Reprogrammable
-Non-Volatile
-100% Tested at Time of Manufacture
*IN-SYSTEM PROGRAMMABLE
-In-System Programmable (ISP™) 5V Only
-Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
-Reprogram Soldered Devices for Faster Prototyping
*OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
-Complete Programmable Device Can Combine Glue Logic and Structured Designs
-Enhanced Pin Locking Capability
-Four Dedicated Clock Input Pins
-Synchronous and Asynchronous Clocks
-Programmable Output Slew Rate Control to Minimize Switching Noise
-Flexible Pin Placement
-Optimized Global Routing Pool Provides Global Interconnectivity
-Lead-Free Package Options

ispLSI1048E125LQI, ispLSI1048E100LQI, ispLSI1048E90LQI, ispLSI1048E70LQI

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Description
The ispLSI 1016EA is a High Density Programmable Logic Device containing 96 Registers, 32 Universal I/O pins, one Dedicated Input pin, two Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP).
The GRP provides complete interconnectivity between all of these elements.
The ispLSI 1016EA features 5V in-system programmability (ISP™) and in-system diagnostic capabilities via an IEEE 1149.1 Test Access Port.
The ispLSI 1016EA offers non-volatile reprogrammability of the logic, as well as the interconnect
to provide truly reconfigurable systems.
A functional superset of the ispLSI 1016 architecture, the ispLSI 1016EA device adds user-selectable 3.3V or 5V I/O and open-drain output options.
The basic unit of logic on the ispLSI 1016EA device is the Generic Logic Block (GLB).
The GLBs are labeled A0, A1...B7 (Figure 1).
There are a total of 16 GLBs in the ispLSI 1016EA device.
Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered.
Inputs to the GLB come from the GRP and a dedicated input.
All of the GLB outputs are brought back into the GRP so that they can be connected to the
inputs of any other GLB on the device.

Features
* HIGH-DENSITY PROGRAMMABLE LOGIC
- 2000 PLD Gates
- 32 I/O Pins, One Dedicated Input
- 96 Registers
- High-Speed Global Interconnect
- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.
- Small Logic Block Size for Random Logic
- Functionally Compatible with ispLSI 1016E
* NEW FEATURES
- 100% IEEE 1149.1 Boundary Scan Testable
- ispJTAG™ In-System Programmable via IEEE 1149.1 (JTAG) Test Access Port
- User-Selectable 3.3V or 5V I/O Supports Mixed- Voltage Systems (VCCIO Pin)
- Open-Drain Output Option
* HIGH-PERFORMANCE E2CMOS® TECHNOLOGY
- fmax = 200 MHz Maximum Operating Frequency
- tpd = 4.5 ns Propagation Delay
- TTL Compatible Inputs and Outputs
- Electrically Erasable and Reprogrammable
- Non-Volatile
- 100% Tested at Time of Manufacture
- Unused Product Term Shutdown Saves Power
* IN-SYSTEM PROGRAMMABLE
- Increased Manufacturing Yields, Reduced Time-to-Market and Improved Product Quality
- Reprogram Soldered Device for Faster Prototyping
* OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS
- Complete Programmable Device Can Combine Glue Logic and Structured Designs
- Enhanced Pin Locking Capability
- Three Dedicated Clock Input Pins
- Synchronous and Asynchronous Clocks
- Programmable Output Slew Rate Control to Minimize Switching Noise
- Flexible Pin Placement
- Optimized Global Routing Pool Provides Global Interconnectivity

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