DESCRIPTION
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities.
The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video.
Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed the S5935 to solve the problem of interfacing applications to the PCI Local bus while offering support for newer PCI chipsets and operating systems. The S5935 is a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5935 can become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec. The S5935 PCI controller also maintains dropin compatibility for upgrading many existent S5933 designs requiring migration into new motherboard architectures, PCI BIOSs and software operating systems.

FEATURES
*PCI 2.1 Compliant Master/Slave Device
*Full 132 Mbytes/sec Transfer Rate
*Supports new Intel 440BX/GX Chipsets
*Supports new WinNT Service Pack 2 & 3
*PCI Bus Operation DC to 33 MHz
*8/16/32 Bit Add-On User Bus
*Four Definable Pass-Thru Data Channels
*Two 32 Byte Internal FIFOs w/DMA
*Synchronous Add-On Bus Operation
*Mail Box Registers w/Byte Level Status
*Direct Mail Box Data Strobe/Interrupts
*Direct PCI & Add-On Interrupt Pins
*Optional Non-Volatile Memory Boot Loading
*Optional Expansion BIOS/POST Code

APPLICATIONS
*High Speed Networking
*Digital Video Applications
*I/O Communications Ports
*High Speed Data Input/Output
*Multimedia Communications
*Memory Interfaces
*High Speed Data Acquisition
*Data Encryption/Decryption
*Intel i960 Interface
*General Purpose PCI Interfacing
*Existent S5933 Design Upgrades*

S5935QF, S5935QRC, S5935TFC
TAG PCI, product

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General description
The ISP1562 is a Peripheral Component Interconnect (PCI)-based, single-chip Universal Serial Bus (USB) host controller. It integrates two Original USB Open Host Controller Interface (OHCI) cores, one Hi-Speed USB Enhanced Host Controller Interface (EHCI) core, and two transceivers that are compliant with Hi-Speed USB and Original USB. The functional parts of the ISP1562 are fully compliant with Universal Serial Bus Specification Rev. 2.0, Open Host Controller Interface Specification for USB Rev. 1.0a, Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0, PCI Local Bus Specification Rev. 2.2, and PCI Bus Power Management Interface Specification Rev. 1.1.
Integrated high performance USB transceivers allow the ISP1562 to handle all Hi-Speed USB transfer speed modes: high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1562 provides two downstream ports, allowing simultaneous connection of USB devices at different speeds.
The ISP1562 is fully compatible with various Operating System (OS) drivers, such as Microsoft Windows standard OHCI and EHCI drivers that are present in Windows XP, Windows 2000 and Red Hat Linux.
The ISP1562 directly interfaces to any 32-bit, 33 MHz PCI bus. Its PCI pins can source 3.3 V. The PCI interface fully complies with PCI Local Bus Specification Rev. 2.2.
The ISP1562 is ideally suited for use in Hi-Speed USB mobile applications and embedded solutions. The ISP1562 uses a 12 MHz crystal.

Features
*Complies with Universal Serial Bus Specification Rev. 2.0
*Supports data transfer at high-speed (480 Mbit/s), full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s)
*Two Original USB OHCI cores comply with Open Host Controller Interface Specification for USB Rev. 1.0a
*One Hi-Speed USB EHCI core complies with Enhanced Host Controller Interface Specification for Universal Serial Bus Rev. 1.0
*Supports PCI 32-bit, 33 MHz interface compliant with PCI Local Bus Specification Rev. 2.2, with support for D3cold standby and wake-up modes; all I/O pins are 3.3 V standard
*Compliant with PCI Bus Power Management Interface Specification Rev. 1.1 for all hosts (EHCI and OHCI), and supports all power states: D0, D1, D2, D3hot and D3cold
*CLKRUN support for mobile applications, such as internal notebook design
*Configurable subsystem ID and subsystem Vendor ID through external EEPROM
*Digital and analog power separation for better ElectroMagnetic Interference (EMI) and
ElectroStatic Discharge (ESD) protection
*Supports hot Plug and Play and remote wake-up of peripherals
*Supports individual power switching and individual overcurrent protection for downstream ports
*Supports partial dynamic port-routing capability for downstream ports that allows sharing of the same physical downstream ports between the Original USB host controller and the Hi-Speed USB host controller
*Uses 12 MHz crystal oscillator to reduce system cost and EMI emissions
*Supports dual power supply: PCI Vaux(3V3) and VCC
*Operates at +3.3 V power supply input
*Low power consumption
*Full industrial operating temperature range from -40 °C to +85 °C
*Full-scan design with high fault coverage (93 % to 95 %) ensures high quality
*Available in LQFP100 package

Applications
*Digital consumer appliances
*Notebook
*PCI add-on card
*PC motherboard
*Set-Top Box (STB)
*Web appliances

ISP1562BE

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DESCRIPTION
The PCI Local bus concept was developed to break the PC data I/O bottleneck and clearly opens the door to increasing system speed and expansion capabilities. The PCI Local bus moves high speed peripherals from the I/O bus and places them closer to the system’s processor bus, providing faster data transfers between the processor and peripherals. The PCI Local bus also addresses the industry’s need for a bus standard which is not directly dependent on the speed, size and type of system processor. It represents the first microprocessor independent bus offering performance more than adequate for the most demanding applications such as full-motion video.
Applied Micro Circuits Corporation (AMCC), the premier supplier of single chip solutions, has developed the S5335 to solve the problem of interfacing applications to the PCI Local bus while offering support for newer PCI chipsets and operating systems. The S5335 is a powerful and flexible PCI controller supporting several levels of interface sophistication. At the lowest level, it can serve simply as a PCI bus Target with modest transfer requirements. For high-performance applications, the S5335 can become a Bus Master to attain the PCI Local bus peak transfer capability of 132 MBytes/sec. The S5335 was designed for 3.3V environment but its inputs/outputs are tolerant to 5V signaling.

FEATURES
*PCI 2.1 Compliant Master/Slave Device
*Full 132 Mbytes/sec Transfer Rate
*PCI Bus Operation DC to 33 MHz
*8/16/32 Bit Add-On User Bus
*3.3V Power Supply
*5V Tolerant I/Os
*Four Definable Pass-Thru Data Channels
*Two 32 Byte Internal FIFOs w/DMA
*Synchronous Add-On Bus Operation
*Mail Box Registers w/Byte Level Status
*Direct Mail Box Data Strobe/Interrupts
*Direct PCI & Add-On Interrupt Pins
*Optional Non-Volatile Memory Boot Loading
*Optional Expansion BIOS/POST Code
*176 Pin LQFP
*Environmental Friendly Lead-Free Package Option

APPLICATIONS
*High Speed Networking
*Digital Video Applications
*I/O Communications Ports
*High Speed Data Input/Output
*Multimedia Communications
*Memory Interfaces
*High Speed Data Acquisition
*Data Encryption/Decryption
*Intel i960 Interface
*General Purpose PCI Interfacing

S5335QF, S5335QFAAB, S5335DK

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Description
PI6C20800S is a PCI Express, high-speed, low-noise differential clock buffer designed to be a companion to PI6C410BS PCIExpress clock generator for Intel server chipsets.
The device distributes the differential SRC clock from PI6C410BS to eight differential pairs of clock outputs either with or without PLL.
The input SRC clock can be divided by 2 when SRC_DIV# is LOW.
The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA.
When input of either SRC_STOP# or PWRDWN# is LOW, the output clocks are Tristated.
When PWRDWN# is LOW, the SDA and SCLK inputs must be Tristated.

Features
* Phase jitter fi lter for PCIe application
* Eight Pairs of Differential Clocks
* Low skew < 50ps
* Low Cycle-to-cycle jitter < 50ps
* Output Enable for all outputs
* Outputs Tristate control via SMBus
* Power Management Control
* Programmable PLL Bandwidth
* PLL or Fanout operation
* 3.3V Operation
* Packaging (Pb-Free & Green):
- 48-Pin SSOP (V)
- 48-Pin TSSOP (A)

PI6C20800SVE
PI6C20800SAE
TAG Buffer, Clock, HCSL, PCI

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GENERAL DESCRIPTION
 PCI 9080 provides a compact, high performance PCI bus master interface for adapter boards and embedded systems.
The programmable local bus of the chip can be configured to directly connect a wide variety of processors, controllers and memory subsystems.
PCI 9080 contains an Intelligent I/O (I2O) messaging unit that allows high performance and compatible software implementations of the I2O bus protocol specification.
Users of the PCI 9060, 9060ES and 9060SD chips may upgrade their products to support I2O, 3.3 Volts and other new features with little or no change to existing hardware and software.
PCI 9080 provides eight programmable FIFOs.
Each operating mode—slave, direct, master, and DMA channel—have dedicated, independent read and write FIFOs.
PCI 9080 also allows a local processor to configure other PCI devices in the system.

FEATURES
• PCI Version 2.1 compliant Bus Master Interface chip for adapters and embedded systems
• I2O Compatible Messaging Unit
• 3.3 or 5 Volt PCI signaling, 5 volt core, low-power CMOS in 208-pin PQFP
• Two independent DMA channels for local bus memory to/from PCI host bus data transfers
• Eight programmable FIFOs for zero wait state burst operation
• PCI Local data transfers up to 132 MB/sec
• Programmable local bus supports nonmultiplexed 32-bit address/data, multiplexed 32 or 16 bit, and slave accesses of 32, 16, or 8 bit local bus devices
• Local bus runs asynchronously to the PCI bus
• Eight 32 bit mailbox and two 32 bit doorbell registers
• Performs Big Endian/Little Endian conversion
• Upward compatibility with PCI 9060/9060ES/9060SD

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GENERAL DESCRIPTION
The ICS9DB202 is a high perfromance 1-to-2 Differential-to-HCSL Jitter Attenuator designed for
use in PCI Express™ systems. In some PCI Express™ systems, such as those found in desktop PCs, the PCI Express™ clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer.
In these systems, a jitter-attenuating device may be necessary in order to reduce high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The ICS9DB202 has two PLL bandwidth modes. In low bandwidth mode, the PLL loop bandwidth is 500kHz. This setting offers the best jitter attenuation and is still high enough to pass a triangular input spread spectrum profile. In high bandwidth mode, the PLL bandwidth is at 1MHz and allows the PLL to pass more spread spectrum modulation.
For serdes which have x10 reference multipliers instead of x12.5 multipliers, each of the two PCI Express™ outputs (PCIEX0:1) can be set for 125MHz instead of 100MHz by configuring the
appropriate frequency select pins (FS0:1).

FEATURES
• Two 0.7V current mode differential HCSL output pairs
• One differential clock input
• CLK and nCLK supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum output frequency: 140MHz
• Input frequency range: 90MHz - 140MHz
• VCO range: 450MHz - 700MHz
• Output skew: 110ps (maximum)
• Cycle-to-cycle jitter: 110ps (maximum)
• RMS phase jitter @ 100MHz, (1.5MHz - 22MHz): 2.42ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant packages
• Industrial temperature information available upon request

ICS9DB202CG
ICS9DB202CGT
ICS9DB202CGLF
ICS9DB202CGLFT
ICS9DB202CF
ICS9DB202CFT
ICS9DB202CFLF
ICS9DB202CFLFT

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Device Overview
The 89HPES5T5 is a member of IDT’s PRECISE™ family of PCI Express switching solutions. The PES5T5 is an 5-lane, 5-port peripheral chip that performs PCI Express Base switching. It provides connectivity and switching functions between a PCI Express upstream port and up to
four downstream ports and supports switching between downstream ports.

Features
◆ High Performance PCI Express Switch
– Five 2.5Gbps PCI Express lanes
– Five switch ports
– Upstream port is x1
– Downstream ports are x1
– Low-latency cut-through switch architecture
– Support for Max Payload Sizes up to 256 bytes
– One virtual channel
– Eight traffic classes
– PCI Express Base Specification Revision 1.1 compliant
◆ Flexible Architecture with Numerous Configuration Options
– Automatic lane reversal on all ports
– Automatic polarity inversion
– Ability to load device configuration from serial EEPROM
◆ Legacy Support
– PCI compatible INTx emulation
– Bus locking
◆ Highly Integrated Solution
– Requires no external components
– Incorporates on-chip internal memory for packet buffering queueing
– Integrates five 2.5 Gbps embedded SerDes with 8B/ encoder/decoder (no separate transceivers needed)
◆ Reliability, Availability, and Serviceability (RAS) Features
– Internal end-to-end parity protection on all TLPs ensures data integrity even in systems that do not implement end-to-
CRC (ECRC)
– Supports ECRC and Advanced Error Reporting
– Supports PCI Express Native Hot-Plug, Hot-Swap capable
– Compatible with Hot-Plug I/O expanders used on PC motherboards
◆ Power Management
– Utilizes advanced low-power design techniques to achieve typical power consumption
– Supports PCI Power Management Interface specification (PCIPM 1.2)
– Unused SerDes are disabled.
– Supports Advanced Configuration and Power Interface Specification, Revision 2.0 (ACPI) supporting active link state
◆ Testability and Debug Features
– Built in Pseudo-Random Bit Stream (PRBS) generator
– Numerous SerDes test modes
– Ability to read and write any internal register via the SMBus
– Ability to bypass link training and force any link into any mode
– Provides statistics and performance counters
TAG PCI, Switch

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Product Highlights
* Non-Transparent PCI-to-PCI bridge technology for high-performance embedded and intelligent I/O applications
* Independent address spaces and asynchronous clocks deliver unparalleled application
flexibility
* 64-bit primary and secondary bus interfaces deliver high performance for data-intensive applications
* Compliant with ACPI and PCI bus power management specifications
* Secondary bus arbitration support for up to nine bus master devices
* Evaluation Design Kit speeds time-to-market
* Fully compliant with Revision 2.3 of the PCI specification including delayed transactions
* Available in 33 and 66 MHz

Product Overview
Intel’s 21555 Non-Transparent PCI-to-PCI bridge chip enables add-in card vendors to deliver high-performance, intelligent option cards and embedded products that previously were not possible. Designed specifically for applications where a processor is used behind a PCI-to-PCI bridge, the 21555 provides a clean architecture for creating a product with multiple processor domains.

Efficient Management of System and Subsystem Resources
The 21555 provides independent primary and secondary address spaces, which allow independent host and local address mapping.
With this key feature, local memory requirements need not impact the host address map. The 21555 performs address translation between the primary and secondary buses, resolving address resource conflicts between the host and local address domains.

 Featuring a subsystem PCI configuration boundary, the 21555 allows the local processor to
have complete PCI configuration control of subsystem devices, without host interference. This
advanced feature also allows the 21555 to present subsystem, such as a RAID controller, as a
single virtual PCI device. An added benefit of this design is the ability to easily identify a single
device driver for the entire subsystem. Another feature of the 21555, a serial ROM interface,
allows manufacturers to customize the 21555 for particular application by pre-loading the ROM
with vendor-specific configuration data.

A Unique Bridge Architecture
Intel’s 21555 is a unique new Non-Transparent PCI-to-PCI bridge solution. The 21555 provides
designers of intelligent controllers and embedded systems with a Non-Transparent PCI to- PCI bridge solution capable of resolving resource conflicts between a PCI-based host system and a PCI-based subsystem. This gives a local processor maximum flexibility in mapping and managing subsystem resources.

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