General Description
The DM74121 is a monostable multivibrator featuring both positive and negative edge triggering with complementary outputs. An internal 2kΩ timing resistor is provided for design convenience minimizing component count and layout problems. this device can be used with a single external capacitor. Inputs (A) are active-LOW trigger transition inputs and input (B) is and active-HIGH transition Schmitttrigger input that allows jitter-free triggering from inputs with
transition rates as slow as 1 volt/second.
A high immunity to VCC noise of typically 1.5V is also provided by internal circuitry at the input stage. To obtain optimum and trouble free operation please read operating rules and one-shot application notes carefully and observe recommendations.

* Triggered from active-HIGH transition or active-LOW transition inputs
* Variable pulse width from 30 ns to 28 seconds
* Jitter free Schmitt-trigger input
* Excellent noise immunity typically 1.2V
* Stable pulse width up to 90% duty cycle
* TTL, DTL compatible
* Compensated for VCC and temperature variations
* Input clamp diodes


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· Available in the Texas Instruments NanoFree™ Package
· Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.65-V to 5.5-V Power-Supply Range
· VCC Isolation Feature – If Either VCC Input Is at GND, Both Ports Are in the High-Impedance
· DIR Input Circuit Referenced to VCCA
· Low Power Consumption, 10-mA Max ICC
· ±24-mA Output Drive at 3.3 V
· Ioff Supports Partial-Power-Down Mode Operation
· Max Data Rates
– 420 Mbps (3.3-V to 5-V Translation)
– 210 Mbps (Translate to 3.3 V)
– 140 Mbps (Translate to 2.5 V)
– 75 Mbps (Translate to 1.8 V)
· Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
· ESD Protection Exceeds JESD 22
– 4000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

 This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.65 V to 5.5 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation between any of the 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes.
 The SN74LVC2T45 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input activate either the B-port outputs or the A-port outputs. The device transmits data from the A bus to the B bus when the B-port outputs are activated, and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

 The SN74LVC2T45 is designed so that the DIR input circuit is supplied by VCCA.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state. NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.


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General Description
 The ADC14V155 is a high-performance CMOS analog-todigital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size.  
 This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14V155 operates from dual +3.3V and +1.8V power supplies and consumes 951 mW of power at 155 MSPS.
 The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A powerdown feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

 The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14V155 can be operated with an external reference. Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable.
 A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles. It is available in a 48-lead LLP package and operates over the industrial temperature range of −40°C to +85°C.

■ 1.1 GHz Full Power Bandwidth
■ Internal sample-and-hold circuit
■ Low power consumption
■ Internal precision 1.0V reference
■ Single-ended or Differential clock modes
■ Clock Duty Cycle Stabilizer
■ Dual +3.3V and +1.8V supply operation (+/- 10%)
■ Power-down and Sleep modes
■ Offset binary or 2's complement output data format
■ LVDS outputs
■ 48-pin LLP package, (7x7x0.8mm, 0.5mm pin-pitch)

Key Specifications
- Resolution 14 Bits
- Conversion Rate 155 MSPS
- SNR (fIN = 70 MHz) 71.7 dBFS (typ)
- SFDR (fIN = 70 MHz) 86.9 dBFS (typ)
- ENOB (fIN = 70 MHz) 11.5 bits (typ)
- Full Power Bandwidth 1.1 GHz (typ)
- Power Consumption 951 mW (typ)

■ High IF Sampling Receivers
■ Wireless Base Station Receivers
■ Power Amplifier Linearization
■ Multi-carrier, Multi-mode Receivers
■ Test and Measurement Equipment
■ Communications Instrumentation
■ Radar Systems


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* Operating Voltage Range of 4.5 V to 5.5 V
* High-Current Outputs Drive Up To 15 LSTTL Loads
* Low Power Consumption, 80-uA Max Icc
* Typical tpd=13ns
* ±6-mA Output Drive at 5V
* Low Input Current of 1uA Max
* Inputs Are TTL-Voltage Compatible
* 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

description/ordering information
These octal buffers and line drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The ’HCT244 devices are organized
as two 4-bit buffers/drivers with separate
output-enable (OE) inputs. When OE is low, the
device passes noninverted data from the A inputs
to the Y outputs. When OE is high, the outputs are
in the high-impedance state.


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General Description
The ’AC/’ACT373 consists of eight latches with TRI-STATE outputs for bus organized system applications. The flip-flops appear transparent to the data when Latch Enable (LE) is HIGH. When LE is LOW, the data that meets the setup time is latched. Data appears on the bus when the Output Enable OE) is LOW. When OE is HIGH, the bus output is in the high impedance state.

* ICC and IOZ reduced by 50%
* Eight latches in a single package
* TRI-STATE outputs for bus interfacing
* Outputs source/sink 24 mA
* ’ACT373 has TTL-compatible inputs
* Standard Microcircuit Drawing (SMD)
— ’AC373: 5962-87555
— ’ACT373: 5962-87556


TAG Latch, Outputs

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General Description
The DM74LS47 accepts four lines of BCD (8421) input data, generates their complements internally and decodes the data with seven AND/OR gates having open-collector outputs to drive indicator segments directly. Each segment output is guaranteed to sink 24 mA in the ON (LOW) state and withstand 15V in the OFF (HIGH) state with a maximum leakage current of 250 mA. Auxiliary inputs provided blanking, lamp test and cascadable zero-suppression functions.


ㅁ Open-collector outputs
ㅁ Drive indicator segments directly
ㅁ Cascadable zero-suppression capability
ㅁ Lamp test input


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The TD74BC574P/TD74BC574F is a high-speed 8-bit flip-flop fabricated with silicon gate Bi-CMOS technology. It achieves the high-speed operation equivalent to the FAST family while
maintaining the Bi-CMOS low-power dissipation. The TD74BC574P/F is a non-inverting flip-flop. Each bit is individually controlled by a clock input (CK) and an output enable input (OE). When the OE input is high, all eight outputs are in the high-impedance state, which facilitates the interface with bus lines. All inputs are equipped with resistors and diodes to protect
against Electrostatic Discharge (ESD).

• High-speed operation ........................ tpd = 8.8 ns (typ.)
• Symmetrical output impedance ....... IOH = −3 mA (max) IOL = 24 A (max)
• Low power dissipation ...................... ICCD = 7 mA (typ.) ICCZ = 10 ?A (typ.)
• Operating temperature range .......... Ta = −40°C to 85°C
• High ESD protection ......................... 2000 V (MIL standard)
• Pin and function compatible with FAST (74F574)

TAG Outputs

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