DESCRIPTION
Maxwell Technologies’ 54LVTH162245 devices are 16-bit (dual-octal) non-inverting 3-state transceivers designed for low-voltage (3.3V) VCC operation, but with the capability to provide a TTL interface to a 5V system environment. These devices can be used as two 8-bit transceivers or one 16-bit transceiver. The devices allow data transmission from the A bus to the B bus or form the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output enable (OE) input can be used to disable the device so that the buses are effectively isolated. The A-port outputs, which are designed to source or sink up to 12 mA, include equivalent 22-Ωseries resistors to reduce overshoot and undershoot.
Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S.

FEATURES
*A-Port outputs have equivalent 22-Ω series resistors, so no external resistors are required
*Support mixed-mode signal operation (5V input and output voltages with 3.3V VCC)
*Support unregulated battery operation down to 2.7V
*TypicalVOLP (output ground bounce) < 0.8V at VCC = 3.3V, TA = 25°C
*IOFF and power-up 3-state support hot insertion
*Bus hold on data inputs eliminates the need for external pullup/pulldown resistors
*Distributed VCC and GND pin configuration minimizes highspeed switching noise
*Flow-through architecture optimizes PCB layout
*Total dose hardness:
-100 krad (Si), depending upon space mission
*Package: 48 pin RAD-PAK® flat pack

54LVTH162245RPFS, 54LVTH162245RPFB, 54LVTH162245RPFE

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DESCRIPTION
The AZP94 is a specialized ÷1 or ÷2 clock generation part including an enable/reset function. The divide ratio is selected with the DIV-SEL pin/pad. When DIV-SEL is open (NC), the AZP94 functions as a standard receiver. If DIV-SEL is connected to VEE, it functions as a ÷2 divider.
Enable (EN) functionality is selected with the EN-SEL pin/pad which has three valid states: open (NC), VEE, or connected to VEE via a 20kΩ ± 20% resistor. Leaving EN-SEL open or connecting it to VEE allows the EN pin/pad to function as an active high CMOS/TTL enable. When EN-SEL is open, an internal 75kΩ pull-up resistor is selected which enables the outputs whenever EN is left open. When EN-SEL is connected to VEE, an internal 75kΩ pulldown resistor is selected which disables the outputs whenever EN is left open.
Connecting the EN-SEL to VEE with a 20kΩ resistor will allow the EN pin/pad to function as an active low PECL/ECL enable with an internal 75kΩ pull-down resistor. In this mode, outputs are enabled when EN is left open (NC). The default logic condition can be overridden by connecting the EN to VCC with an external resistor of ≤20kΩ. If the enable signal is CMOS (rail-to-rail) and the logic sense is active low (EN-SEL connected to VEE with a 20kΩ resistor), the EN pin/pad voltage swing must be reduced using two external resistors. Contact the factory for details.
When the AZP94 is disabled, the Q and Q¯ outputs are forced LOW and the input buffer is powered down to minimize feed through. This feature allows tristate compatible parallel output connections. Multiple AZP94 chip outputs can be wired together. Since both outputs are forced LOW in the disable mode, an enabled AZP94 can drive the output lines without interference from the unselected units. In addition, the AZP94 can be used in parallel connection with PECL/ECL parts whose outputs are high impedance when disabled.
The EN pin/pad also functions as a reset when the ÷2 mode is selected. In the ÷2 mode, the counter resets when the outputs are disabled.

FEATURES
• Green and RoHS Compliant / Lead (Pb) Free Package Available
• 3.0V to 5.5V Operation
• Selectable Divide Ratio
• Selectable Enable Polarity and Threshold (CMOS/TTL or PECL)
• Tristate Compatible Outputs
• Input Buffer Powers Down when Disabled
• Selectable Input Biasing
• High Bandwidth for ≥1GHz
• Available in a MLP 8 (2x2) Package
• IBIS Model File Available on Arizona Microtek Website

AZP94NAG, AZP94XP

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FEATURES
· Maximum Sample Rate: 125 MSPS
· 14-Bit Resolution with No Missing Codes
· 3.5 dB Coarse Gain and up to 6 dB TPrraodgera-Omfmf able Fine Gain for SNR/SFDR
· Parallel CMOS and Double Data Rate (DDR) LVDS Output Options
· Supports Sine, LVCMOS, LVPECL, LVDS Clock Inputs, and Clock Amplitude Down to 400
mVPP
· Clock Duty Cycle Stabilizer
· Internal Reference with Support for External Reference
· No External Decoupling Required for References
· Programmable Output Clock Position and Drive Strength to Ease Data Capture
· 3.3-V Analog and 1.8-V to 3.3-V Digital Supply
· 32-QFN Package (5 mm ´ 5 mm)
· Pin Compatible 12-Bit Family (ADS612X)

APPLICATIONS
· Wireless Communications Infrastructure
· Software Defined Radio
· Power Amplifier Linearization
· 802.16d/e
· Test and Measurement Instrumentation
· High Definition Video
· Medical Imaging

ADS6142IRHBR
ADS6142IRHBRG4
ADS6142IRHBT

TAG CMOS, DDR, Outputs

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FEATURES
· Maximum Sample Rate: 125 MSPS
· 11-Bit Resolution With No Missing Codes
· 84 dBc SFDR at Fin = 50 MHz
· 67.1 dBFS SNR at Fin = 50 MHz
· 92 dB Crosstalk
· Parallel CMOS and DDR LVDS Output Options
· 3.5 dB Coarse Gain and Programmable Fine Gain up to 6 dB for SNR/SFDR Trade-Off
· Digital Processing Block With:
– Offset Correction
– Fine Gain Correction, in Steps of 0.05 dB
– Decimation by 2/4/8
– Built-in and Custom Programmable 24-Tap Low/High /Band Pass Filters
· Supports Sine, LVPECL, LVDS & LVCMOS
· CClloocckksD&utAymCpyclilteudSetaDboilwiznerto 400 mVPP
· Internal Reference; Supports External Reference also
· 64-QFN Package (9mm ´ 9mm)
· Pin Compatible 14-bit and 12-bit Family (ADS62P4X/ADS62P2X)

APPLICATIONS

· Wireless Communications Infrastructure
· Software Defined Radio
· Power Amplifier Linearization
· 802.16d/e
· Medical Imaging
· Radar Systems
· Test and Measurement Instrumentation

DESCRIPTION
ADS62P15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.
ADS62P15 includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.
Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62P15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated.
Nevertheless, the device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62P45
ADS62P44
ADS62P43
ADS62P42

TAG ADC, CMOS, dual, Outputs

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Features
■ ICC and IOZ reduced by 50%
■ Multiplexer expansion by tying outputs together
■ Inverting 3-STATE outputs
■ Outputs source/sink 24mA
■ TTL-compatible inputs

General Description
 The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. Four bits of data from two sources can be selected using a common data select input. The four outputs present the selected data in the complement (inverted) form.
 The outputs may be switched to a high impedance state with a HIGH on the common Output Enable (OE) input, allowing the outputs to interface directly with bus-oriented systems.

Functional Description
The ACT258 is a quad 2-input multiplexer with 3-STATE outputs. It selects four bits of data from two sources under control of a common Select input (S). When the Select input is LOW, the I
0x inputs are selected and when Select is HIGH, the I1x inputs are selected.
 The data on the selected inputs appears at the outputs in inverted form. The ACT258 is the logic implementation of a 4-pole, 2-position switch where the position of the switch is determined by the logic levels supplied to the Select input. The logic equations for the outputs are shown below:
Za= OE • (I1a • S + I0a • S)
Zb= OE • (I1b • S + I0b • S)
Zc= OE • (I1c • S + I0c • S)
Zd= OE • (I1d • S + I0d • S)
When the Output Enable input (OE) is HIGH, the outputs are forced to a high impedance state. If the outputs of the 3-STATE devices are tied together, all but one device must be in the high impedance state to avoid high currents that would exceed the maximum ratings.
 Designers should ensure that Output Enable signals to 3-STATE devices whose outputs are tied together are designed so there is no overlap.

74ACT258SC
74ACT258SJ
74ACT258MTC

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Features
• 32,768 channel x 32,768 channel non-blocking digital Time Division Multiplex (TDM) switch at
65.536 Mbps or 32.768 Mbps or using a combination of rates
• 16,384 channel x 16,384 channel non-blocking digital TDM switch at 16.384 Mbps
• 8,192 channel x 8,192 channel non-blocking digital TDM switch at 8.192 Mbps
• High jitter tolerance with multiple input clock sources and frequencies
• Up to 64 serial TDM input streams, divided into 32 groups with 2 input streams per group
• Up to 64 serial TDM output streams, divided into 32 groups with 2 output streams per group
• Per-group input and output data rate conversion selection at 65.536 Mbps, 32.768 Mbps,
16.384 Mbps and 8.192 Mbps. Input and output data group rates can differ
• Per-group input bit delay for flexible sampling point selection
• Per-group output fractional bit advancement
• Two sets of output timing signals for interfacing additional devices
• Per-channel A-Law/µ-Law Translation
• Per-channel constant or variable throughput delay for frame integrity and low latency applications
• Per-stream Bit Error Rate (BER) test circuits
• Per-channel high impedance output control
• Per-channel force high output control
• Per-channel message mode
• Control interface compatible with Intel and Motorola 16 bit non-multiplexed buses
• Connection memory block programming
• Supports ST-BUS and GCI-Bus standards for input and output timing
• IEEE 1149.1 (JTAG) test port
• 3.3 V I/O with 5V tolerant inputs; 1.8 V core voltage

Applications
• Large Switching Platforms
• Central Office Switches
• Wireless Base Stations
• Multi-service Access Platforms
• Media Gateways

Description
 The ZL50075 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The device can switch 64 kbps and Nx64 kbps TDM channels from any input stream to any output stream. With a number of enhanced features, the ZL50075 is designed for high capacity voice and data switching applications.

 The ZL50075 has 64 input and 64 output data streams which can operate at 8.192 Mbps, 16.384 Mbps, 32.768 Mbps or 65.536 Mbps. The large number of inputs and outputs maintains full 32 K x 32 K channel switching capacity at bit rates of 65 Mbps and 32 Mbps. Up to 32 input and output data streams may operate at 65 Mbps. Up to 64 input and output data streams may operate at 32 Mbps, 16 Mbps or 8 Mbps. The data rate can be independently set in groups of 2 input or output streams. In this way it is possible to provide rate conversion from
input data channel to output data channel.

 The ZL50075 uses a master clock (CKi0) and frame pulse (FPi0) to define the TDM data stream frame boundary and timing. A high speed system clock is derived internally from CKi0 and FPi0. The input and output data streams can independently reference their timings to the input clock or to the internal system clock.
The ZL50075 has a variety of user configurable options designed to provide flexibility when data streams are connected to multiple TDM components or circuits. These include:
• Variable input bit delay and output advancement, to accommodate delays and frame offsets of streams connected through different data paths
• Two timing outputs, CKo1 - 0 and FPo1 - 0, which can be configured independently to provide a variety of clock and frame pulse options
• Support of both ST-BUS and GCI-Bus formats
- The ZL50075 also has a number of value added features for voice and data applications:
• Per-channel variable delay mode for low latency applications and constant delay mode for frame integrity applications:
• Per-channel A-Law/µ-Law Conversions for both voice and data
• 64 separate Pseudo-random Bit Sequence (PRBS) test circuits; one per stream. This provides an integrated Bit
Error Rate (BER) test capability to facilitate data path integrity checking

 The ZL50075 has two major modes of operation: Connection Mode (normal) and Message Mode. In Connection Mode, data bytes received at the TDM inputs are switched to timeslots in the output data streams, with mapping controlled by the Connection Memories. Using Zarlink's Message Mode capability, microprocessor data can be broadcast to the output data streams on a per-channel basis. This feature is useful for transferring control and status information to external circuits or other TDM devices.

 A non-multiplexed microprocessor port provides access to the internal Data Memory, Connection Memory and Control Registers used to program ZL50075 options. The port is configurable to interface with either 16 bit Motorola or Intel-type microprocessors.
The mandatory requirements of IEEE 1149.1 standard are supported via the dedicated Test Access Port.

ZL50075GAC
ZL50075GAG2

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Features
■ High speed: fMAX=140MHz (Typ.) at TA=25°C
■ High noise immunity: VIH=2.0V, VIL=0.8V
■ Power down protection is provided on all inputs andoutputs
■ Low power dissipation: ICC=4µA (Max.) @ TA=25°C
■ Pin and function compatible with 74HCT374

General Description
 The VHCT374A is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a high impedance state.

 Protection circuits ensure that 0V to 7V can be applied to the input and output
(1) pins without regard to the supply voltage. This device can be used to interface 3V to 5V
systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched supply and input voltages.
Note:
1. Outputs in OFF-State.

74VHCT374AM
74VHCT374ASJ
74VHCT374AMTC

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• Isolated
• Fixed Frequency (600 kHz)
• High Efficiency
• High Power Density
• Low Cost
• Output Voltage Trim
• Basic Insulation
• UL60950-1 Recognized (UL/cUL)
• Input Under Voltage Lockout
• Output Over Voltage Shutdown
• OCP/SCP
• Over Temperature Protection
• Remote On/Off (option)
• Positive/Negative Remote Sense
• Through Hole and SMT (option)


Description
The xRSB-50T series are isolated dc/dc converters that operate from a nominal 48 Vdc source. These units will provide up to 60 W of output power from a nominal 48 Vdc input. These units are designed to be highly efficient and low cost. Features include remote on/off, over current protection and under voltage lockout. These converters are provided in an industry standard sixteenth brick package.

xRSB-50TV2L xRSB-50TV20
xRSB-50TV5L xRSB-50TV50
xRSB-50TV8L xRSB-50TV80
xRSB-50T02L xRSB-50T025
xRSB-50T03L xRSB-50T033
xRSB-50T05L xRSB-50T050
xRSB-50T12L xRSB-50T120

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Features
■ High Speed: tPD=5.4ns (typ) at VCC=5V
■ High noise immunity: VNIH=VNIL=28% VCC(Min.)
■ Power down protection is provided on all inputs
■ Low power dissipation: ICC=4µA (Max) @ TA=25°C
■ Pin and function compatible with 74HC374

General Description
 The VHC374 is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This 8-bit D-type flip-flop is controlled by a clock input (CP) and an output enable input (OE). When the OE input is HIGH, the eight outputs are in a HIGH impedance state.

 An input protection circuit ensures that 0V to 7V can be applied to the input pins without regard to the supply voltage. This device can be used to interface 5V to 3V systems and two supply systems such as battery back up. This circuit prevents device destruction due to mismatched
supply and input voltages.

74VHC374M
74VHC374SJ
74VHC374MTC

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Features
• Three channel video reconstruction filters
• YUV/RGB filters
• 2:1 Mux inputs for multiple RGB/YUV inputs
• Selectable 8MHz or 30MHz 6th order filters for RGB (YUV) applications
• 8MHz 6th order Y, C filters with composite summer
• DC coupled input, AC coupled output
• All outputs can drive AC coupled 150Ω loads and provide 6dB of gain
• Dual multiplexed inputs
• 0.6% differential gain with 0.2° differential phase
• 36dB/octave roll-off on all channels

Description
 The FMS6419 offers comprehensive filtering for set top box or DVD applications. This part consists of a triple 6th order filter with selectable 30MHz or 8MHz frequencies.
 A 2-to-1 multiplexer is provided on each filter channel. The triple filters are intended for either YUV or RGB signals. All channels accept DC coupled ground-referenced 1V signals.
 The filters provide 2Vpp signals into AC coupled terminated loads. The low-pass filters are powered by 3.3V and the outputs by 5.0V.

Applications
• Cable Set top boxes
• Satellite Set top boxes
• DVD players
• HDTV
• Personal Video Recorders (PVR)
• Video On Demand (VOD)

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