Description
The NAND08GW3C2A and NAND16GW3C2A are multilevel cell (MLC) devices from the NAND Flash 2112-byte page family of non-volatile Flash memories. The NAND08GW3C2A and the NAND16GW3C2A have a density of 8- and 16-Gbit, respectively. The NAND16GW3C2A is composed of two 8-Gbit dice; each die can be accessed independently using two Chip Enable and two Ready/Busy signals. The devices operate from a 3 V VDD power supply.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 input/output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
Each block can be programmed and erased over 10,000 cycles (with ECC on). The device also has hardware security features; a write protect pin is available to give hardware protection against Program and Erase operations.
The devices feature an open-drain, ready/busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the ready/busy pins of several memories to be connected to a single pull-up resistor. The memory array is split into 2 planes of 2048 blocks each. This multiplane architecture makes it possible to program 2 pages at a time (one in each plane) or to erase 2 blocks at a time (one in each plane), dividing by two the average program and erase times.
The devices have the Chip Enable “Don’t Care” feature, which allows code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the Read operation.
There is the option of a unique identifier (serial number), which allows the NAND08GW3C2A and the NAND16GW3C2A to be uniquely identified. It is subject to an NDA (non-disclosure agreement) and is, therefore, not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.
The devices are available in TSOP48 (12 × 20 mm) and LGA52 (12 x 17 x 0.65 mm) packages. To meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are lead-free. In compliance with JEDEC Standard JESD97, the category of second level interconnect is marked on the package and on the inner box label. The maximum ratings related to soldering conditions are also marked on the inner box label.
The devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ‘1’.

Features
*High density multilevel cell (MLC) Flash memory
-Up to 16 Gbit memory array
-Up to 512 Mbit spare area
-Cost-effective solutions for mass storage applications
*NAND interface
-x 8 bus width
-Multiplexed address/data
*Supply voltage: VDD = 2.7 to 3.6 V
*Page size: (2048 + 64 spare) bytes
*Block size: (256K + 8K spare) bytes
*Multiplane architecture
-Array split into two independent planes
-Program/erase operations can be performed on both planes at the same time
*Page read/program
-Random access: 60 μs (max)
-Sequential access: 25 ns (min)
-Page program operation time: 800 μs (typ)
*Multipage program time (2 pages): 800 μs (typ)
*Fast block erase
-Block erase time: 2.5 ms (typ)
*Multiblock erase time (2 blocks): 2.5 ms (typ)
*Status register
*Electronic signature
*Serial number option
*Chip enable ‘don’t care’
*Data protection
-Hardware program/erase locked during power transitions
*Development tools
-Error correction code models
-Bad block management and wear leveling algorithm
-HW simulation models
*Data integrity
-10,000 program/erase cycles (with ECC)
-10 years data retention
*ECOPACK® packages available

NAND16GW3C4A, NAND08GW3C2AN1E, NAND16GW3C2AN1E, NAND08GW3C4AN1E

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General Description
The eKF5250 provides a high-performance interface to bridge USB and NAND Flash compliance device which can be used to implement of flash memory storage device with USB interface. It contains a 8-bit RISC processor to greatly reduce firmware development work.
The eKF5250 has a phase Lock Loop(PLL) embedded. The PLL provided all clocks needed in this Controller. It needs an externally provided clock operating in 2 Mhz.
The eKF5250 can control up to 4 pieces of NAND Flash memory. The flash capacity can be 16M bytes up to 256M bytes. And these chips can be any combination. It has been optimized to support Toshiba and Samsung flash memory designs. The controller has write-protected ability to prevent writing data to flash. For read/write operation, the controller can achieve 1000KB /800KB throughput.
This controller can operate in Win XP, Win2000, Windows ME without any driver installation.

Features
*USB Specification v1.1 Compliant
*USB Mass Storage Class v1.0 Compliant
*Support 12 Mbits/s Full Speed Serial Data Transmission
*Support USB Mass Storage Class Bulk-Only Spec.
*USB bus-powered capability
*Build in PLL used to generate clock for USB. And MCU.
*Total 3 Endpoints. Endpoint 0 is the default control endpoint. Endpoint 1 is the Bulk-in endpoint. Endpoint 2 is the Bulk-out endpoint.
*4K x 13 on chip ROM(Program).
*Support wear leveling
*Support write-protected ability.
*Higher reliability : ECC on the fly
*Support ping-pong buffer(Two 536x8 bits) for data transfer to/from NAND Flash
*Support 4 pieces of NAND Flash.memory
*8 Level stack for subroutine nesting.
*1 LED sink pin with internal serial resistor.
*One 8 bits general purpose timer.
*Watchdog Timer with its own on-chip RC oscillator
*Supports saving power mode(SLEEP MODE)
*MCU run at 16MHz.
*Performance:Read(1000K Bytes/s), Write(800K Bytes/s) Max.
*Package:SSOP28

Applications
*NAND Flash Controller
*Smart Media Controller

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Description
NAND08GAH0A and NAND16GAH0D are embedded Flash memory storage solutions with MultiMediaCard interface (eMMC™). The eMMC™ was developed for universal low cost data storage and communication media. They can be considered as high speed MultiMediaCards embedded in LFBGA169 12 x 16 x 1.4 mm, 0.5 mm pitch package instead of an MMC. The devices are fully compatible with MMC bus and hosts.
NAND08GAH0A and NAND16GAH0D communications are made through an advanced 13-pin bus. The bus can be either 1-bit, 4-bit, or 8-bit bus width. The devices operate in highspeed mode at clock frequencies equal or higher than 20 MHz. The communication protocol is defined as a part of this MMC standard and referred to as MultiMediaCard mode. For compatibility with existing controllers the devices may offer, in addition to the MultiMediaCard mode, an alternate communication protocol which is based on the SPI standard.
The devices are designed to cover a wide area of applications such as smart phones, cameras, organizers, PDA, digital recorders, MP3 players, pagers, electronic toys, etc. They feature high performance, low power consumption, low cost and high density.
To meet the requirements of embedded high density storage media and mobile applications, Numonyx NAND08GAH0A and NAND16GAH0D support both 3 V supply voltage (VCC), and 1.8 V/3 V input/output voltage (VCCQ).
The devices have a built-in intelligent controller which manages interface protocols, data storage and retrieval, wear leveling, bad block management, garbage collection, internal ECC.
In order to meet environmental requirements, Numonyx offers the NAND08GAH0A and NAND16GAH0D in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an Numonyx trademark.

Features
*Packaged NAND Flash memory with MultiMediaCard interface
*1, 2 Gbytes of formatted data storage
*eMMC/MultiMediaCard system specification, compliant with V4.1
*Full backward compatibilty with previous MultiMediaCard system specification
*Bus mode
–High-speed MultiMediaCard protocol
–SPI protocol
–Three different data bus widths:1 bit, 4 bits, 8 bits
–Data transfer rate: up to 52 Mbyte/s
*Operating voltage range:
–VCCQ =1.8 V/3 V
–VCC = 3 V
*Supported clock frequencies: 0 to 52 MHz
*Multiple Block Read (x 8 at 52 MHz): up to 3.5 Mbyte/s
*Multiple Block Write (x 8 at 52 MHz): up to 8.5 Mbyte/s
*Power dissipation
–Standby current: down to 200 μA
–Read current: down to 30 mA
–Write current: down to 30 mA
*Error free memory access
–Internal enhanced data management algorithm (wear levelling, bad block management, garbage collection)
–Internal error correction code
*Data integrity
–Data reliability: less than 1 non-recoverable error per 1014 bits read
–Endurance: more that 2,000,000 Program/Erase cycles
*Security
–Password protection of data
–Built-in write protection (permanent or temporary)

NAND16GAH0D, NAND08GAH0AZA5E, NAND16GAH0AZA5E, NAND08GAH0DZA5E
TAG NAND

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Description
The NAND Flash 528 Byte/ 264 Word Page is a family of non-volatile Flash memories that uses the Single Level Cell (SLC) NAND cell technology. It is referred to as the Small Page family. The NAND512R3A2C, NAND512R4A2C, NAND512W3A2C, and NAND512W4A2C have a density of 512 Mbits and operate with either a 1.8V or 3V voltage supply. The size of a Page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare) depending on whether the device has a x8 or x16 bus width.
The address lines are multiplexed with the Data Input/Output signals on a multiplexed x8 or x16 Input/Output bus. This interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint.
To extend the lifetime of NAND Flash devices it is strongly recommended to implement an Error Correction Code (ECC). The use of ECC correction allows to achieve up to 100,000 program/erase cycles for each block. A Write Protect pin is available to give a hardware protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the Program/Erase/Read (P/E/R) Controller is currently active. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor.
A Copy Back command is available to optimize the management of defective blocks. When a Page Program operation fails, the data can be programmed in another page without having to resend the data to be programmed.
The devices are available in the following packages:
*TSOP48 12 x 20mm
*VFBGA63 (9 x 11 x 1mm, 6 x 8 ball array, 0.8mm pitch)
In order to meet environmental requirements, Numonyx offers the devices in ECOPACK® packages. ECOPACK packages are Lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label.
All devices have the Chip Enable Don't Care option, which allows the code to be directly downloaded by a microcontroller, as Chip Enable transitions during the latency time do not stop the read operation.
A Serial Number option, allows each device to be uniquely identified. The Serial Number options is subject to an NDA (Non Disclosure Agreement) and so not described in the datasheet. For more details of this option contact your nearest Numonyx Sales office.

Features
*High density NAND Flash memories
– 512 Mbit memory array
– Cost effective solutions for mass storage applications
*NAND interface
– x 8 or x 16 bus width
– Multiplexed Address/ Data
*Supply voltage: 1.8 V, 3.0 V
*Page size
– x 8 device: (512 + 16 spare) bytes
– x 16 device: (256 + 8 spare) words
*Block size
– x 8 device: (16 K + 512 spare) bytes
– x 16 device: (8 K + 256 spare) words
*Page Read/Program
– Random access: 12 μs (3 V)/15 μs (1.8 V) (max)
– Sequential access: 30 ns (3 V)/50 ns (1.8 V) (min)
– Page Program time: 200 μs (typ)
*Copy Back Program mode
*Fast Block Erase: 2 ms (typ)
*Status Register
*Electronic signature
*Chip Enable ‘don’t care’
*Serial Number option
*Hardware Data Protection
– Program/Erase locked during Power transitions
*Data integrity
– 100,000 Program/Erase cycles (with ECC)
– 10 years Data Retention
*ECOPACK® packages
*Development tools
– Error Correction Code models
– Bad Blocks Management and Wear Leveling algorithms
– Hardware simulation models

NAND512R4A2C, NAND512W3A2C, NAND512W4A2C

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Hardware Features
* Low-power operation
* Single input voltage: Internal voltage regulation for analog, digital, and I/O power
* Operates with a single 12 MHz clock
* Internal PLL clock multiplier
* Power button pin, software-controlled power-off
* USB Full Speed hardware
* NAND FLASH interface with ECC
* I/O for user interface
* High-quality on-chip stereo DAC with no phase error between channels
* Stereo earphone driver capable of driving a 30­ load
* Lead-free RoHS-compliant package (Green)

Firmware Features
* Implements USB Mass Storage Device and Audio Device
* NAND FLASH handling with error correction, block remapping, and wear levelling
* Default player application in firmware
– Decodes Ogg Vorbis, sound level normalization using Replay Gain
– Pause / Play
– Volume control
– Next / Previous Song
– Rewind and Fast Forward
– Random Play
– EarSpeaker Spatial Processing
* Bass and treble controls for customized player
* NAND FLASH boot for customized player
* SPI FLASH boot for special applications
* UART for debugging and special applications

Description
VS1000 is a single-chip Ogg Vorbis (license-free audio codec) player. VS1000 contains a high-performance low-power DSP core VS DSP4, NAND FLASH interface, Full Speed USB port, general purpose I/O pins, SPI, UART, as well as a highquality variable-sample-rate stereo DAC, and an earphone amplifier and a common voltage buffer.
VS1000 firmware implements a default player that reads and plays files from the NAND FLASH.
The player can be customized or replaced by using boot from NAND FLASH.
When connected to USB, the firmware implements USB Mass Storage Device protocol or acts as an Audio Device, providing a single-chip USB headphone application.
EarSpeaker spatial processing provides more natural sound in headphone listening conditions. It widens the stereo image and positions the sound sources outside the listener’s head.
SPI EEPROM can be used to load code in applications that do not use NAND FLASH.

TAG Flash, NAND, USB

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General description
The 74AUP1G00 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.
Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.
This device ensures a very low static and dynamic power consumption across the entire VCC range from 0.8 V to 3.6 V.
This device is fully specified for partial Power-down applications using IOFF.
The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.
The 74AUP1G00 provides the single 2-input NAND function.

Features
* Wide supply voltage range from 0.8 V to 3.6 V
* High noise immunity
* Complies with JEDEC standards:
 + JESD8-12 (0.8 V to 1.3 V)
 + JESD8-11 (0.9 V to 1.65 V)
 + JESD8-7 (1.2 V to 1.95 V)
 + JESD8-5 (1.8 V to 2.7 V)
 + JESD8-B (2.7 V to 3.6 V)
* ESD protection:
 + HBM JESD22-A114-C Class 3A. Exceeds 5000 V
 + MM JESD22-A115-A exceeds 200 V
 + CDM JESD22-C101-C exceeds 1000 V
* Low static power consumption; ICC = 0.9 mA (maximum)
* Latch-up performance exceeds 100 mA per JESD 78 Class II
* Inputs accept voltages up to 3.6 V
* Low noise overshoot and undershoot < 10 % of VCC
* IOFF circuitry provides partial Power-down mode operation
* Multiple package options
* Specified from -40 °C to +85 °C and -40 °C to +125 °C

74AUP1G00GW
74AUP1G00GM
74AUP1G00GF

TAG Gate, NAND

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Description
 The MC10/100EP05 is a 2−input differential AND/NAND gate.
 The device is functionally equivalent to the EL05 and LVEL05 devices. With AC performance much faster than the LVEL05 device, the EP05 is ideal for applications requiring the fastest
AC performance available.
 The 100 Series contains temperature compensation.

Features
• 220 ps Typical Propagation Delay
• Maximum Frequency > 3 GHz Typical
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• Pb−Free Packages are Available

MC10EP05D MC10EP05DG MC10EP05DR2 MC10EP05DR2G MC10EP05DT MC10EP05DTG
MC10EP05DTR2 MC10EP05DTR2G MC10EP05MNR4 MC10EP05MNR4G MC100EP05D
MC100EP05DG MC100EP05DR2 MC100EP05DR2G MC100EP05DT MC100EP05DTG
MC100EP05DTR2 MC100EP05DTR2G MC100EP05MNR4 MC100EP05MNR4G
TAG Input, NAND

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General Description
The MM74HC00 NAND gates utilize advanced silicon-gate CMOS technology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS integrated circuits. All gates have buffered outputs. All devices have high noise immunity and the ability to drive 10 LS-TTL loads. The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to VCC and ground.

Features

* Typical propagation delay: 8 ns
* Wide power supply range: 2–6V
* Low quiescent current: 20 mA maximum (74HC Series)
* Low input current: 1 ㎂ maximum
* Fanout of 10 LS-TTL loads

MM74HC00M MM74HC00SJ MM74HC00MTC MM74HC00N MTC14
TAG Gate, NAND, Quad

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High–Performance Silicon–Gate CMOS
The MC74HC132A is identical in pinout to the LS132. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs.
The HC132A can be used to enhance noise immunity or to square up slowly changing waveforms.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V
• Low Input Current: 1.0 mA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard No. 7A
• Chip Complexity: 72 FETs or 18 Equivalent Gates

MC74HC132AN MC74HC132AD MC74HC132ADR2
TAG Input, NAND

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